HT48E10 Holtek Semiconductor, HT48E10 Datasheet - Page 6

• Manufacturer Part Number: HT48E10
• Description: I/O Type 8-Bit MTP MCU
• Manufacturer: Holtek Semiconductor

In System Programming
In system programming allows programming and repro-
gramming of HT48EXX microcontroller on application
circuit board, this will save time and money, both during
development in the lab. Using a simple 3-wire interface,
the ISP communicates serially with the HT48EXX
microcontroller, reprogramming program memory and
EEPROM data memory on the chip.
Program Memory - ROM
The program memory is used to store the program in-
structions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
1024 14 bits, addressed by the program counter and ta-
ble pointer.
Certain locations in the program memory are reserved
for special usage:
Note: *9~*0: Table location bits
Rev. 1.50
Pin Name Function
PA0
PA4
RES
VDD
VSS
TABRDC [m]
TABRDL [m]
Instruction
@7~@0: Table pointer bits
SDATA
SCLK
RESET
VDD
VSS
ISP Pin Assignments
Program Memory
P9
*9
1
Serial data input/output
Serial clock input
Device reset
Power supply
Ground
P8
*8
1
Description
@7
@7
*7
@6
@6
*6
Table Location
6
Table Location
@5
@5
*5
P9~P8: Current program counter bits
Location 000H
This area is reserved for program initialization. After a
chip reset, the program always begins execution at lo-
cation 000H.
Location 004H
This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
Location 008H
This area is reserved for the timer/event counter inter-
rupt service program. If a timer interrupt results from a
timer/event counter overflow, and if the interrupt is en-
abled and the stack is not full, the program begins exe-
cution at location 008H.
Table location
Any location in the program memory space can be
used as look-up tables. The instructions TABRDC
[m] (the current page, one page=256 words) and
the lower-order byte to the specified data memory,
and the higher-order byte to TBLH (08H). Only the
destination of the lower-order byte in the table is
well-defined, the other bits of the table word are trans-
ferred to the lower portion of TBLH, any unused bits
will have uncertain values. The Table Higher-order
byte register (TBLH) is read only. The table pointer
(TBLP) is a read/write register (07H), which indicates
the table location. Before accessing the table, the lo-
cation must be placed in the TBLP. The TBLH is read
only and cannot be restored. If the main routine and
the ISR (Interrupt Service Routine) both employ the
table read instruction, the contents of the TBLH in the
main routine are likely to be changed by the table read
instruction used in the ISR. Errors can occur. In other
words, using the table read instruction in the main rou-
tine and the ISR simultaneously should be avoided.
However, if the table read instruction has to be applied
in both the main routine and the ISR, the interrupt is
supposed to be disabled prior to the table read in-
struction. It will not be enabled until the TBLH has
been backed up. All table related instructions require
two cycles to complete the operation. These areas
may function as normal program memory depending
on the requirements.
TABRDL [m] (the last page) transfer the contents of
@4
@4
*4
@3
@3
*3
@2
@2
*2
October 31, 2006
@1
@1
www.DataSheet4U.com
*1
HT48E10
@0
@0
*0