HT48E10 Holtek Semiconductor, HT48E10 Datasheet - Page 14

• Manufacturer Part Number: HT48E10
• Description: I/O Type 8-Bit MTP MCU
• Manufacturer: Holtek Semiconductor

Input/Output Ports
There are 19 bidirectional input/output lines in the
microcontroller, labeled from PA to PC, which are
mapped to the data memory of [12H], [14H], [16H], re-
spectively. All of these I/O ports can be used for input
and output operations. For input operation, these ports
are non-latching, that is, the inputs must be ready at the
T2 rising edge of instruction MOV A,[m] (m=12H, 14H
or 16H). For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC) to control the input/output configuration. With this
control register, CMOS output or Schmitt trigger input
with or without pull-high resistor structures can be re-
configured dynamically under software control. To func-
tion as an input, the corresponding latch of the control
register must write a 1 . The input source also depends
on the control register. If the control register bit is 1 ,
the input will read the pad state. If the control register bit
is 0 , the contents of the latches will move to the inter-
nal bus. The latter is possible in the read-modify-write
instruction.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H and 17H.
After a chip reset, these input/output lines remain at high
levels or in a floating state (depending on the pull-high
The I/O functions of PB0/PB1 are shown below.
Note:
Rev. 1.50
PB0 I/O
PB1 I/O
PB0 Mode
PB1 Mode
PB0 Data
PB1 Data
PB0 Pad Status
PB1 Pad Status
I input, O output, D, D
B buzzer option, BZ or BZ, x don t care
C CMOS output
x
x
x
x
I
I
I
I
O
C
D
D
x
x
I
I
0
, D
1
data,
O
C
D
D
x
x
I
I
O
B
x
0
x
0
I
I
14
options). Each bit of these input/output latches can be
set or cleared by SET [m].i and CLR [m].i (m=12H,
14H or 16H) instructions.
Some instructions first input data and then follow the
output operations. For example, SET [m].i , CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the de-
vice. The highest 5-bit of port C is not physically imple-
mented; on reading them a 0 is returned whereas writing
results in no operation. See Application note.
There is a pull-high option available for all I/O lines (bit
option). Once the pull-high option of an I/O line is se-
lected, the I/O line has a pull-high resistor. Otherwise,
the pull-high resistor is absent. It should be noted that a
non-pull-high I/O line operating in input mode will cause
a floating state.
The PB0 and PB1 are pin-shared with BZ and BZ, re-
spectively. If the BZ/BZ option is selected, the output
signal in output mode of PB0/PB1 will be the PFD signal
generated by the Timer/Event Counter 0 overflow sig-
nal. The input mode always remain in its original func-
tions. Once the BZ/BZ option is selected, the buzzer
output signals are controlled by the PB0 data register
only.
O
B
B
x
1
x
I
I
D
D
D
D
O
O
C
C
0
1
0
1
O
O
B
C
D
D
0
0
O
O
B
C
D
B
D
1
October 31, 2006
www.DataSheet4U.com
O
O
B
B
0
0
0
x
HT48E10
O
O
B
B
B
B
1
x