HT46R74D-1 Holtek Semiconductor, HT46R74D-1 Datasheet - Page 21

• Manufacturer Part Number: HT46R74D-1
• Description: Dual Slope A/D Type MCU
• Manufacturer: Holtek Semiconductor

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If PA3 is selected to be a PFD output, there are two
types of selections. One is to use PFD0 as the PFD out-
put, the other is to use PFD1 as the PFD output. PFD0
and PFD1 are the timer overflow signals of the
Timer/Event Counter 0 and Timer/Event Counter 1 re-
spectively. No matter what the operation mode is, writ-
ing a 0 to ET0I or ET1I disables the related interrupt
service. When the PFD function is selected, executing a
while executing a CLR [PA].3 instruction will disable
the PFD output.
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register also re-
loads that data to the timer/event counter. But if the
timer/event counter is running, data written to the
timer/event counter will be loaded only to the timer/event
counter preload register. The timer/event counter still
continues its operation until an overflow occurs.
When the timer/event counter is read, the clock will be
blocked to avoid errors, which may result in a counting
error, and should be taken into account by the program-
mer. It is strongly recommended to load a desired value
into the TMR0/TMR1 register first, before turning on the
related timer/event counter, for proper operation since
the initial value of TMR0/TMR1 is unknown. After this
procedure, the timer/event function can be operated
normally.
Bit0~bit2 of TMR0C can be used to define the pre-scal-
ing stages of the timer/event counter internal clock. The
overflow signal of timer/event counter can be used to
generate the PFD signal.
Input/Output Ports
There are 10 bidirectional input/output lines in the
microcontroller, labeled as PA and PB, which are
mapped to the data memory of [12H] and [14H] respec-
tively. All of these I/O ports can be used for input and
output operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at the T2
rising edge of instruction MOV A,[m] (m=12H or 14H).
For output operations, all the data is latched and re-
mains unchanged until the output latch is rewritten.
Each I/O line has its own control register, known as PAC
and PBC, to control the input/output configuration. With
this control register, either CMOS outputs or Schmitt
trigger inputs with or without pull-high resistor structures
can be reconfigured dynamically under software control.
To function as an input, the corresponding latch of the
control register must be written with a 1 . The input
source also depends on the control register. If the con-
trol register bit is 1 , the input will read the pad state. To
function as an output the the control register bit should
be set to 0 . The latter is possible in the read-mod-
ify-write instruction.
Rev. 1.10
SET [PA].3 instruction will enable the PFD output
21
After a device reset, these input/output lines will default
to inputs and remain at a high level or in a floating state,
depending upon the pull-high configuration options.
Each bit of these input/output latches can be set or
cleared by a SET [m].i and CLR [m].i (m=12H or
14H) instruction.
Some instructions first input data and then follow the
output operations. For example, SET [m].i , CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device.
Each I/O port has a pull-high option. Once a pull-high
option is selected, the I/O port has a pull-high resistor
connected. Take note that a non-pull-high I/O port setup
as an input mode will be in a floating condition.
Pins PA0, PA1, PA3, PA4, PA5, PA6 and PA7 are
pin-shared with BZ, BZ, PFD, TMR0, TMR1, INT0 and
INT1 pins respectively.
PA0 and PA1 are pin-shared with BZ and BZ signal, re-
spectively. If the BZ/BZ configuration option is selected,
the output signals in the output mode of PA0/PA1 will be
the buzzer signal. The input mode always retains its
original function. Once the BZ/BZ configuration option is
selected, the buzzer output signals are controlled by the
PA0 data register.
The PA0/PA1 I/O function is shown below.
Note:
It is recommended that if there are unused or not
bonded out I/O lines then they should be setup as output
pins using software instructions to avoid consuming
power. If setup as inputs and left floating this may result
in unnecessary increased power consumption.
PA0 I/O
PA1 I/O
PA0 Mode
PA1 Mode
PA0 Data
PA1 Data
PA0 Pad Status
PA1 Pad Status
I input; O output
D, D0, D1 Data
B buzzer option, BZ or BZ
X don t care
C CMOS output
X X C B B C B B B B
X C X X X C C C B B
X X D 0
X D X X X D1 D D X X
I
I
I
I
O
D
I
I
O O O O O O O O
D 0 B D
I
I
I
I
1 D
I
I D
HT46R74D-1
O O O O O
January 11, 2007
0
0
1
D D 0 B
0
0 B 0 B
1
0
1