HT46R74D-1 Holtek Semiconductor, HT46R74D-1 Datasheet - Page 10

• Manufacturer Part Number: HT46R74D-1
• Description: Dual Slope A/D Type MCU
• Manufacturer: Holtek Semiconductor

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The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
The status register is 8 bits wide and contains, a carry
flag (C), an auxiliary carry flag (AC), a zero flag (Z), an
overflow flag (OV), a power down flag (PDF), and a
watchdog time-out flag (TO). It also records the status
information and controls the operation sequence.
Except for the TO and PDF flags, the status register bits
can be altered by instructions similar to other registers.
Data written into the status register does not alter the TO
or PDF flags. Operations related to the status register,
however, may yield different results from those in-
tended. The TO and PDF flags can only be changed by
a Watchdog Timer overflow, a device power-up, or
clearing the Watchdog Timer and executing the HALT
instruction. The Z, OV, AC, and C flags reflect the status
of the latest operations.
On entering the interrupt sequence or executing a sub-
routine call, the status register will not be automatically
pushed onto the stack. If the contents of the status regis-
ter is important, and if the subroutine is likely to corrupt
the status register, the programmer should take precau-
tions and save it properly.
Interrupts
The device provides two external interrupts, two internal
timer/event counter interrupts and the ADC interrupt.
The interrupt control register INTC0, and interrupt con-
trol register INTC1, both contain the interrupt control bits
that are used to set the enable/ disable status and inter-
rupt request flags.
Once an interrupt subroutine is serviced, other inter-
rupts are all blocked, by clearing the EMI bit. This pre-
vents further interrupt nesting. Other interrupt requests
may take place during this interval, but only the interrupt
Rev. 1.10
Bit No.
6~7
0
1
2
3
4
5
Label
PDF
OV
AC
TO
C
Z
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a ro-
tate through carry instruction.
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
PDF is cleared by either a system power-up or executing the CLR WDT instruction.
PDF is set by executing the HALT instruction.
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction.
TO is set by a WDT time-out.
Unused bit, read as 0
Status (0AH) Register
10
request flag will be recorded. If a certain interrupt re-
quires servicing within the service routine, the EMI bit
and the corresponding bit of INTC0 or INTC1 may be
set in order to permit interrupt nesting to take place.
Once the stack is full, the interrupt request will not be ac-
knowledged, even if the related interrupt is enabled, un-
til the Stack Pointer is decremented. If immediate
service is desired, the stack should be prevented from
becoming full.
All interrupts will provide a wake-up function. As an in-
terrupt is serviced, a control transfer occurs by pushing
the contents of the program counter onto the stack fol-
lowed by a branch to a subroutine at the specified loca-
tion in the Program Memory. Only the contents of the
program counter is pushed onto the stack. If the con-
tents of the accumulator or of the status register is al-
tered by the interrupt service program which corrupts
the desired control sequence, the contents should be
saved in advance.
External interrupts are triggered by an edge transition
on pin INT0 or INT1. A configuration option determines
the type of edge transition, high to low, low to high, or
both low to high and high to low. Their related interrupt
request flags are EIF0; bit 4 of INTC0, and EIF1; bit 5 of
INTC0, must also be set. After the interrupt is enabled, if
the stack is not full and the external interrupt is active, a
subroutine call to location 04H or 08H occurs. The inter-
rupt request flag, EIF0 or EIF1, and EMI bits will be
cleared to disable other maskable interrupts.
The internal Timer/Event Counter 0 interrupt is gener-
ated when the Timer/Event Counter 0 interrupt request
flag is set, which is bit T0F; bit 6 of INTC0. This occurs
when the timer overflows. After the interrupt is enabled,
if the stack is not full, and the T0F bit is set, a subroutine
call to location 0CH occurs. The related interrupt re-
quest flag, T0F, will be reset, and the EMI bit will be
cleared to disable other maskable interrupts. The inter-
rupt for Timer/Event Counter 1 operates in a similar
Function
HT46R74D-1
January 11, 2007