HT46R74D-1 Holtek Semiconductor, HT46R74D-1 Datasheet - Page 11

• Manufacturer Part Number: HT46R74D-1
• Description: Dual Slope A/D Type MCU
• Manufacturer: Holtek Semiconductor

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manner but its related interrupt request flag is T1F,
which is bit 4 of INTC1, and its subroutine call location is
10H.
The A/D converter interrupt is generated when the A/D
converter interrupt request flag, ADF; bit 5 of INTC1 is
set. This occurs when an A/D conversion process has
completed. After the interrupt is enabled, if the stack is
not full, and the ADF bit is set, a subroutine call to loca-
tion 14H occurs. The related interrupt request flag, ADF,
is reset and the EMI bit is cleared to disable further
maskable interrupts.
The real time clock interrupt is generated when the real
time clock interrupt request flag, RTF; bit 6 of INTC1, is
set. After the interrupt is enabled, if the stack is not full,
and the RTF bit is set, a subroutine call to location 18H
occurs. The related interrupt request flag, RTF, is reset
and the EMI bit is cleared to disable further maskable in-
terrupts.
During the execution of an interrupt subroutine, other
maskable interrupt acknowledgments are all held until
the RETI instruction is executed or the EMI bit and the
related interrupt control bit are set both to 1 (if the stack
is not full). To return from the interrupt subroutine, a
instruction sets the EMI bit and enables an interrupt ser-
vice, but a RET instruction does not.
Rev. 1.10
RET or RETI instruction may be invoked. A RETI
Bit No.
Bit No.
3, 7
0
1
2
3
4
5
6
7
0
1
2
4
5
6
Label
Label
EADI
ERTI
EEI0
EEI1
ET0I
EIF0
EIF1
ET1I
ADF
RTF
EMI
T0F
T1F
Control the master (global) interrupt (1=enabled; 0=disabled)
Control the external interrupt 0 (1=enabled; 0=disabled)
Control the external interrupt 1 (1=enabled; 0=disabled)
Control the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)
External interrupt 0 request flag (1=active; 0=inactive)
External interrupt 1 request flag (1=active; 0=inactive)
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
For test mode used only.
Must be written as 0 ; otherwise may result in unpredictable operation.
Control the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)
Control the ADC interrupt (1=enabled; 0:disabled)
Control the real time clock interrupt (1=enabled; 0:disabled)
Unused bit, read as 0
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
ADC request flag (1=active; 0=inactive)
Real time clock request flag (1=active; 0=inactive)
INTC0 (0BH) Register
INTC1 (1EH) Register
11
Interrupts occurring in the interval between the rising
edges of two consecutive T2 pulses are serviced on the
latter of the two T2 pulses if the corresponding interrupts
are enabled. In the case of simultaneous requests, the
priorities in the following table apply. These can be
masked by resetting the EMI bit.
Once an interrupt request flag has been set, it remains
in the INTC1 or INTC0 register until the interrupt is ser-
viced or cleared by a software instruction.
It is recommended that a program should not use the
because interrupts often occur in an unpredictable man-
ner or require to be serviced immediately in some appli-
cations. During that period, if only one stack is left, and
enabling the interrupts is not well controlled, executing a
nal control sequence.
CALL subroutine within the interrupt subroutine. This is
call in the interrupt subroutine may damage the origi-
External interrupt 0
External interrupt 1
Timer/Event Counter 0 overflow
Timer/Event Counter 1 overflow
ADC interrupt
Real time clock interrupt
Function
Function
Interrupt Source
HT46R74D-1
Priority
January 11, 2007
1
2
3
4
5
6
Vector
0CH
04H
08H
10H
14H
18H