74ABT16500 Fairchild Semiconductor, 74ABT16500 Datasheet
74ABT16500
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74ABT16500 Summary of contents
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... MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74ABT16500CMTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code. ...
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Logic Diagram www.fairchildsemi.com 2 ...
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Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to CC Ground Pin Input Voltage (Note 5) Input Current (Note 5.0 mA Voltage Applied to Any Output in the ...
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DC Electrical Characteristics Symbol Parameter V Quiet Output Maximum Dynamic V OLP OL V Quiet Output Minimum Dynamic V OLV OL V Minimum HIGH Level Dynamic Output Voltage OHV V Minimum HIGH Level Dynamic Input Voltage IHD V Maximum LOW ...
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AC Operating Requirements Symbol Parameter t (H) Setup Time ( CLKAB S t (H) Hold Time ( CLKAB H t (H) Setup Time ( CLKBA S t (H) ...
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Skew Symbol Parameter t Pin to Pin Skew OSHL (Note 16) HL Transitions t Pin to Pin Skew OSLH (Note 16) LH Transitions t Duty Cycle PS (Note 17) LH–HL Skew t Pin to Pin Skew OST (Note 16) LH/HL ...
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AC Loading *Includes jig and probe capacitance. FIGURE 1. Standard AC Test Load Amplitude 3.0V FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 5. Propagation Delay, Pulse Width Waveforms ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide www.fairchildsemi.com Package Number MS56A 8 ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE ...