FAN6520B Fairchild Semiconductor, FAN6520B Datasheet - Page 9

• Manufacturer Part Number: FAN6520B
• Description: Single Synchronous Buck PWM Controller
• Manufacturer: Fairchild Semiconductor

FAN6520B Rev. 1.0.3
Depending upon the whether there is a load application
or a load removal, the response time to a load transient
(I
approximate response time interval for application and
removal of a transient load:
where T
positive I
removal (negative I
can be either at the application or removal of load. Be
sure to check both of these equations at the minimum
and maximum output levels for the worst case response
time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the volt-
age overshoot across the MOSFETs. Use small ceramic
capacitors for high-frequency decoupling and bulk
capacitors to supply the current needed each time Q1
turns on. Place the small ceramic capacitors physically
close to the MOSFETs and between the drain of Q1 and
the source of Q2. The important parameters for the bulk
input capacitor are the voltage rating and the RMS cur-
rent rating. For reliable operation, select the bulk capaci-
tor with voltage and current ratings above the maximum
input voltage and the largest RMS current required by
the circuit. The capacitor voltage rating should be at least
1.25 times greater than the maximum input voltage and a
voltage rating of 1.5 times is a conservative guideline.
The RMS current rating requirement (I
capacitor of a buck regulator is:
where the converter duty cycle;
through-hole design, several electrolytic capacitors may
be needed. For surface-mount designs, solid tantalum
capacitors can be used, but caution must be exercised
with regard to the capacitor’s surge current rating. The
capacitors must be capable of handling the surge current
at power-up. Some capacitor series available from repu-
table manufacturers are surge current tested.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(C
Selection of these components should be done after the
high-side MOSFET has been chosen. The required
capacitance is determined using the following equation:
STEP
BOOT
I
C
RMS
T
T
BOOT
) is different. The following equations give the
RISE
FALL
) and the internal diode, as shown in Figure 1.
RISE
STEP
=
=
=
I
=
L
is the response time to the application of a
, and T
----------------------------- -
V
L I
------------------------
--------------------- -
L I
IN
V
V
D D
Q
OUT
BOOT
–
STEP
–
G
STEP
STEP
V
FALL
OUT
2
). The worst case response time
is the response time to a load
D
=
V
--------------
V
RMS
OUT
IN
) for the input
. For a
(2)
(3)
9
where Q
FET, and
high-side MOSFET drive. To prevent loss of gate drive,
the bootstrap capacitance should be at least 50 times
greater than the C
secutive cycles, then LDRV is turned on for ~1.6µs to
charge the bootstrap capacitor.
Thermal Considerations
Total device dissipation:
where P
P
FET driver.
Where P
rising and falling edges respectively:
where:
Where Q
As described in the equations above, the total power
consumed in driving the gate is divided in proportion to
the resistances in series with the MOSFET's internal
gate node as shown in Figure 8.
R
R
many designs. Note that the introduction of R
reduce driver power dissipation, but excess R
cause errors in the “adaptive gate drive” circuitry. For
more information please refer to Fairchild app note
AN-6003, “Shoot-through” in Synchronous Buck Con-
verters.
HDRV
G
E
P
P
P
P
P
P
is the polysilicon gate resistance, internal to the FET.
is the external gate drive resistor implemented in
D
Q
HDRV
Q1
H R
H F
BOOT
= P
= V
represents internal power dissipation of the upper
= Q
(http://www.fairchildsemi.com/an/AN/AN-6003.pdf)
Q
G
H(R)
G1
Q
CC
=
= P
=
Figure 8. Driver Dissipation Model
represents quiescent power dissipation:
R
R
is the total gate charge of the high-side MOS-
G1
V
+ P
HUP
HDN
is total gate charge of Q1 for its applied V
P
P
BOOT
and P
HDRV
H(R)
Q1
Q1
2.7mA
HDRV
SW
V
GS(Q1)
ISS
------------------------------------------- -
R
-------------------------------------------
R
H(F)
is the voltage droop allowed on the
P
HDN
HUP
+ P
H(F)
of Q1. If FB is < 800mV for 32 con-
are internal dissipations for the
R
R
LDRV
+
+
HDN
HUP
F
R
R
SW
R
E
E
E
+
+
R
R
G
G
G
R
G
www.fairchildsemi.com
Q1
E
E
S
may
can
GS
(7)
(8)
(4)
(5)
(6)
(9)
.