IDT70T3509M Integrated Device Technology, IDT70T3509M Datasheet - Page 5

• Manufacturer Part Number: IDT70T3509M
• Description: High-speed 2.5v 1024k X 36 Synchronous Dual-port Static Ram With 3.3v Or 2.5v Interface
• Manufacturer: Integrated Device Technology

Truth Table I—Read/Write and Enable Control
NOTES:
1. "H" = V
2. ADS, CNTEN, REPEAT = V
3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
Truth Table II—Address Counter Control
NOTES:
1. "H" = V
2. Read and write operations are controlled by the appropriate setting of R/W, CE
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE
5. The address counter advances if CNTEN = V
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
7. Address A
OE
Address
IDT70T3509M
High-Speed 2.5V
X
X
X
X
X
X
X
X
X
X
X
H
X
L
L
L
L
L
L
L
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
of a A
A
state when using the REPEAT function.
19
An
X
X
X
is actively driven from 0-to-1 or 1-to-0 and held as needed at the appropriate address boundaries for full depth counter operation and that A
CLK
19
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
IH,
IH,
X
is 0, while for physical addresses 80000
"L" = V
"L" = V
19
Previous
Address
Internal
must be managed as part of a full depth counter implementation using the IDT70T3509M. For physical addresses 00000
An + 1
CE
An
H
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
IL,
IL,
0
"X" = Don't Care.
"X" = Don't Care.
CE
1024K x 36 Dual-Port Synchronous Static RAM
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
Address
1
Internal
An + 1
An + 1
Used
An
An
IH
.
BE
X
X
X
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
3
CLK
BE
X
X
X
H
H
H
H
H
H
H
H
H
X
X
↑
↑
↑
↑
L
L
L
L
L
L
2
IL
BE
X
X
X
H
H
H
H
H
H
H
H
H
X
X
ADS
L
L
L
L
L
L
on the rising edge of CLK, regardless of all other memory control signals including CE
H
H
X
1
L
H
(4)
through FFFFF
BE
X
X
X
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
CNTEN
0
X
X
L
H
(5)
R/W
X
X
X
X
X
X
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
REPEAT
the value of A
L
H
H
H
ZZ
X
X
(4)
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
(6)
6.42
5
I/O
Byte 3
High-Z
Active
Active
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
0
D
D
D
D
D
, CE
D
D
D
D
D
OUT
OUT
OUT
I/O
I/O
19
27-35
I/O
IN
IN
IN
I/O
I/O
(n+1)
(n+1)
0
is 1. The user needs to keep track of the device counter and make sure that
1
, CE
(3)
(n)
(n)
, BEn and OE.
(1,2)
1
and BEn
I/O
External Address Used
Counter Enabled—Internal Address generation
External Address Blocked—Counter disabled (An + 1 reused)
Counter Set to last valid ADS load
Byte 2
High-Z
Active
Active
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
D
D
D
D
D
D
OUT
OUT
OUT
18-26
IN
IN
IN
(1,2,3,4)
High-Z
Active
Active
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Byte 1
I/O
D
D
D
D
D
D
OUT
OUT
OUT
9-17
IN
IN
IN
Byte 0
High-Z
Active
Active
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
I/O
D
D
D
D
D
D
OUT
OUT
OUT
Commercial Temperature Range
IN
IN
IN
0-8
MODE
Deselected–Power Down
Not Allowed
Not Allowed
Read Byte 0 Only
Read Byte 1 Only
Read Byte 2 Only
Read Byte 3 Only
Read Lower 2 Bytes Only
Read Upper 2 Bytes Only
Read All Bytes
Outputs Disabled
Sleep Mode
All Bytes Deselected
Write to Byte 0 Only
Write to Byte 1 Only
Write to Byte 2 Only
Write to Byte 3 Only
Write to Lower 2 Bytes Only
Write to Upper 2 bytes Only
Write to All Bytes
H
0
through 7FFFF
, CE
(7)
19
1
MODE
, BEn.
is in the appropriate
H
5682 tbl 02
5682 tbl 03
the value