IDT70T3509M Integrated Device Technology, IDT70T3509M Datasheet - Page 11

• Manufacturer Part Number: IDT70T3509M
• Description: High-speed 2.5v 1024k X 36 Synchronous Dual-port Static Ram With 3.3v Or 2.5v Interface
• Manufacturer: Integrated Device Technology

Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE
NOTES:
1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.
2. ADS = V
3. The output is disabled (High-Impedance state) by CE
4. Addresses do not have to be accessed sequentially since ADS = V
5. If BE
6. "x" denotes Left or Right port. The diagram is with respect to that port.
Timing Waveform of Read Cycle for Flow-Through Output
(FT/PIPE
IDT70T3509M
High-Speed 2.5V
Truth Table 1.
are for reference use only.
ADDRESS
DATA
n
ADDRESS
was HIGH, then the appropriate Byte of DATA
DATA
CLK
R/
CE
CE
BE
IL
OUT
OE
, CNTEN and REPEAT = V
W
0
1
n
CLK
(4)
R/
(1)
CE
BEn
CE
OUT
OE
W
'X'
"X"
0
1
(4)
(1)
= V
= V
t
1024K x 36 Dual-Port Synchronous Static RAM
t
t
t
SW
SA
SC
SB
An
IH
t
t
t
t
SC
SB
SW
t
SA
t
t
t
HW
An
HC
HB
HA
IL
(1 Latency)
)
(1,2)
)
t
t
CH2
t
t
t
HW
HC
HB
HA
(1,2,6)
IH
t
.
CH1
t
CKLZ
t
CYC2
t
t
CD1
CKLZ
t
CYC1
t
CL2
OUT
(1)
0
An + 1
t
CL1
= V
for Qn + 2 would be disabled (High-Impedance state).
An + 1
IH
, CE
t
CD2
1
Qn
= V
t
DC
IL
IL
constantly loads the address on the rising edge of the CLK; numbers
, BE
6.42
n
11
= V
IH
t
An + 2
following the next rising edge of the clock. Refer to
SB
(5)
Qn
An + 2
t
HB
t
DC
Qn + 1
t
OHZ
Qn + 1
t
OHZ
t
t
OE
OLZ
t
An + 3
SC
(3)
t
t
An + 3
SC
SB
t
(3)
HC
Commercial Temperature Range
Qn + 2
t
t
HC
HB
t
t
OE
t
OLZ
DC
(5)
t
CKHZ
Qn + 2
5682 drw 05
5682 drw 06
(5)
,
,