IDT70T3509M Integrated Device Technology, IDT70T3509M Datasheet - Page 13

• Manufacturer Part Number: IDT70T3509M
• Description: High-speed 2.5v 1024k X 36 Synchronous Dual-port Static Ram With 3.3v Or 2.5v Interface
• Manufacturer: Integrated Device Technology

Timing Waveform of Pipelined Read-to-Write-to-Read (OE = V
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE
3. Addresses do not have to be accessed sequentially since ADS = V
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE
3. Addresses do not have to be accessed sequentially since ADS = V
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
IDT70T3509M
High-Speed 2.5V
use only.
are for reference use only.
0
0
, BE
, BE
ADDRESS
DATA
ADDRESS
DATA
DATA
n
n
, and ADS = V
DATA
, and ADS = V
CLK
R/
CE
CE
BE
OUT
OE
CLK
R/
CE
CE
BE
OUT
W
IN
0
1
n
W
IN
(3)
0
1
n
(3)
1024K x 36 Dual-Port Synchronous Static RAM
IL
IL
; CE
t
t
t
t
; CE
SB
SC
SW
SA
t
t
t
t
SB
SW
SC
SA
An
An
1
1
, CNTEN, and REPEAT = V
, CNTEN, and REPEAT = V
t
t
t
t
HW
t
HC
HA
t
t
HB
t
HW
HC
HA
t
HB
CH2
t
(1)
CH2
t
t
CYC2
CYC2
READ
(1)
t
t
READ
CL2
CL2
An +1
An +1
t
CD2
t
CD2
Qn
t
OHZ
IH
IH
. "NOP" is "No Operation".
.
(4)
Qn
t
t
t
SD
SW
Dn + 2
SW
An + 2
An + 2
IL
IL
constantly loads the address on the rising edge of the CLK; numbers
t
constantly loads the address on the rising edge of the CLK; numbers are for reference
t
t
HW
HW
HD
NOP
6.42
13
t
CKHZ
(4)
WRITE
t
SD
Dn + 2
An + 3
Dn + 3
An + 2
t
HD
WRITE
An + 3
An + 4
t
CKLZ
t
CKLZ
Commercial Temperature Range
READ
An + 4
READ
An + 5
t
CD2
t
CD2
5682 drw 11
IL
Qn + 3
5682 drw 12
Qn + 4
)
(2)
,
,
(2)