IDT70T3509M Integrated Device Technology, IDT70T3509M Datasheet - Page 19

• Manufacturer Part Number: IDT70T3509M
• Description: High-speed 2.5v 1024k X 36 Synchronous Dual-port Static Ram With 3.3v Or 2.5v Interface
• Manufacturer: Integrated Device Technology

Functional Description
RAM interface. Registered inputs provide minimal set-up and hold times
on address, data, and all critical control inputs. All internal registers are
clocked on the rising edge of the clock signal, however, the self-timed
internal write pulse width is independent of the cycle time.
chronous bus interfacing. Counter enable inputs are also provided to stall
the operation of the address counters for fast interleaved
memory applications.
cycle will power down the internal circuitry to reduce static power
consumption. Multiple chip enables allow easier banking of multiple
IDT70T3509Ms for depth expansion configurations. Two cycles are
required with CE
Width Expansion
width. Through combining the control signals, the devices can be grouped
as necessary to accommodate applications needing 72-bits or wider.
IDT70T3509M
High-Speed 2.5V
The IDT70T3509M provides a true synchronous Dual-Port Static
An asynchronous output enable is provided to ease asyn-
The IDT70T3509M can be used in applications requiring expanded
The combination of a HIGH on CE
0
LOW and CE
1024K x 36 Dual-Port Synchronous Static RAM
1
HIGH to re-activate the outputs.
0
and a LOW on CE
1
for one clock
6.42
19
Sleep Mode
mode on both ports. The sleep mode pin on both ports is asynchronous
and active high. During normal operation, the ZZ pin is pulled low. When
ZZ is pulled high, the port will enter sleep mode where it will meet lowest
possible power conditions. The sleep mode timing diagram shows the
modes of operation: Normal Operation, No Read/Write Allowed and Sleep
Mode.
to sleep and after recovering from sleep. Clocks must also meet cycle high
and low times during these periods. Three cycles prior to asserting ZZ
(ZZx = V
must be disabled via the chip enable pins. If a write or read operation occurs
during these periods, the memory array may be corrupted. Validity of data
out from the RAM cannot be guaranteed immediately after ZZ is asserted
(prior to being in sleep). When exiting sleep mode, the device must be in
Read mode (R/Wx = V
enable must be valid for one full cycle before a read will result in the output
of valid data.
disconnects its internal clock buffer. The external clock may continue to run
without impacting the RAMs sleep current (I
high-Z state while in sleep mode. All inputs are allowed to toggle. The RAM
will not be selected and will not perform any reads or writes.
The IDT70T3509M is equipped with an optional sleep or low power
For normal operation all inputs must meet setup and hold times prior
During sleep mode the RAM automatically deselects itself. The RAM
IH
) and three cycles after de-asserting ZZ (ZZx = V
IH
)when chip enable is asserted, and the chip
Commercial Temperature Range
ZZ
). All outputs will remain in
IL
), the device