CMR3000-D0X VTI Hamlin, CMR3000-D0X Datasheet - Page 13

• Manufacturer Part Number: CMR3000-D0X
• Description: Cmr3000-d0x Block Diagram With Digital Spi And I 2 C Interface
• Manufacturer: VTI Hamlin

4.1.4 Output register data refresh
4.2 I
4.2.1
4.2.1.1
4.2.1.2
VTI Technologies Oy
Myllynkivenkuja 6
P.O. Box 27
FI-01621 Vantaa
www.vti.fi
2
I
C Interface
2
C frame format
I
I
2
2
C write mode
C read mode
Figure 6. MOSI_SDA pin change during SCK_SCL high state engages I
In cases with multiple slaves in SPI bus it is recommended that I2C transmission is disabled by
setting I2C_DIS bit to '1' in CRTL register. After CMR3000 start up the I2C_DIS bit is always 0 (I
transmission enabled).
When the CSB is pulled ‘0’, the latest data is available in the output registers. Output register data
refresh is enabled only when CSB is ‘1’.
I
master is defined as a micro controller providing the serial clock (SCL), and the slave as any
integrated circuit receiving the SCL clock from the master. The CMR3000 sensor always operates
as a slave device in master-slave operation mode. When using an SPI interface, a hardware
addressing is used (slaves have dedicated CSB signals), the I
addressing (slave devices have dedicated bit patterns as addresses). The default I
address for CMR3000 is 1Eh or 1Fh (pre-programmed during CMR3000 production). LSB bit of the
I2C address is according to MISO pin state.
The CMR3000 is compatible to the Philips I
interface are:
In I
to be written.
The read mode operates as described in Philips I
content of the register which address is defined in I2C read frame. Read data is acknowledged by
I
2
2
C is a 2-wire serial interface. It consists of one master device and one or more slave devices. The
C master.
2
C write mode, the first 8 bits after device address define the CMR3000 internal register address
-
-
-
-
-
-
7-bit addressing, CMR3000 I
Supports standard mode and fast mode
Start / Restart / Stop
Slave transceiver mode
Designed for low power consumption
Multiple read operation mode (decrement reading)
•
•
reading of any register decrements data address by one even if only one
register is read
from register address 0Ch address jumps to 11h
Doc.Nr. 82112900.A.02
2
C device address is TBD
2
C specification V2.1. Main used features of the I
2
C specification. I
2
C interface uses a software based
2
C read operation returns the
2
C transmission.
CMR3000-D0X Series
2
C device
Rev. A.02
13/ 26
2
2
C
C