HM-6561 Intersil Corporation, HM-6561 Datasheet - Page 6

• Manufacturer Part Number: HM-6561
• Description: 256 x 4 CMOS RAM
• Manufacturer: Intersil Corporation

Timing Waveforms
NOTE: 1. Device selected only if both S1 and S2 are low, and deselected if either S1 or S2 are high.
The HM-6561/883 Read Cycle is initiated on the falling edge
of E. This signal latches the input address word into on-chip
registers. Minimum address setup and hold times must be
met. After the required hold time, the address lines may
change state without affecting device operation. In order to
read the output data E, S1 and S2 must be low and W must
be high. The output data will be valid at access time
(TELQV).
REFERENCE
TIME
REFERENCE
-1
0
1
2
3
4
5
S1, S2
TIME
DQ
W
A
E
PREVIOUS DATA
E
H
H
L
L
HIGH
TSHQZ
S1
(4)
H
X
H
X
L
L
L
(7) TAVEL
(6) TEHEL
INPUTS
-1
W
H
H
H
H
H
X
X
HIGH Z
VALID
0
TELAX
(8)
FIGURE 1. READ CYCLE
A
X
V
X
X
X
X
V
(2) TAVQV
HM-6561/883
(1) TELQV
TRUTH TABLE
6-122
OUTPUT
TSLQX
1
DQ
The HM-6561/883 has output data latches that are con-
trolled by E. On the rising edge of E the present data is
latched and remains latched until E falls. Either or both S1 or
S2 may be used to force the output buffers into a high
impedance state.
(5) TELEH
X
V
V
Z
Z
Z
Z
(4)
Memory Disabled
Cycle Begins, Addresses are Latched
Output Enabled
Output Valid
Output Latched
Device Disabled, Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)
(17) TELEL
VALID DATA LATCHED
2
3
FUNCTION
(7) TAVEL
TSHQZ
(6) TEHEL
(4)
4
HIGH Z
5