ISL98001 Intersil Corporation, ISL98001 Datasheet - Page 7

• Manufacturer Part Number: ISL98001
• Description: Triple Video Digitizer
• Manufacturer: Intersil Corporation

R
R
P
S
/G
/G
DATACLK
HSYNC
Video In
P
S
DATACLK
/B
/B
Analog
HSYNC
HS
Video In
G
R
P
S
B
Analog
[7:0]
[7:0]
P
P
P
HS
OUT
[7:0]
[7:0]
[7:0]
IN
OUT
IN
P
0
P
1
P
7
0
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
P
FIGURE 4. 24-BIT 4:2:2 OUTPUT MODE (FOR YUV SIGNALS)
2
The HSYNC edge (programmable leading or trailing) that the DPLL is locked to.
The sampling phase setting determines its relative position to the rest of the AFE’s output signals
P
1
t
HSYNCin-to-HSout
P
t
HSYNCin-to-HSout
3
P
2
8.5 DATACLK Pipeline Latency
= 7.5ns + (PHASE/64 +10.5)*t
P
FIGURE 5. 48-BIT OUTPUT MODE
4
P
= 7.5ns + (PHASE/64 +8.5)*t
3
ISL98001
P
5
P
4
P
6
Width and Polarity
P
Programmable
5
PIXEL
Width and Polarity
P
Programmable
7
PIXEL
P
6
P
8
P
7
P
9
P
8
G
B
0
0
P
(U
10
(Y
o
o
P
)
)
9
G
R
P
1
1
11
(Y
(V
D
D
P
1
1
)
)
0
1
10
G
B
2
P
2
(U
12
(Y
P
2
2
)
)
11
March 8, 2006
D
D
2
3
FN6148.3
P
12