ISL98001 Intersil Corporation, ISL98001 Datasheet - Page 11

• Manufacturer Part Number: ISL98001
• Description: Triple Video Digitizer
• Manufacturer: Intersil Corporation

Pin Descriptions
HSYNC
VSYNC
V
VREG
SYMBOL
V
VREG
COREADC
VS
V
GND
GND
GND
BYPASS
V
CORE
NC
V
V
V
PLL
OUT
A
D
X
OUT
OUT
D
OUT
A
X
IN
6, 11, 18, 20, 29,
MQFP PIN #(s)
3, 5, 8, 10, 15,
17, 21, 23, 27,
54, 67, 77, 89,
32, 43, 51, 53,
66, 76, 78, 88,
98, 108, 110,
99, 111, 124
52, 79, 109
120, 123
4, 9, 16
1, 2, 63
30, 36
126
127
128
35
38
37
65
64
31
42
(Continued)
11
3.3V digital output. Artificial VSYNC output aligned with pixel data. VS
the trailing edge of HS
3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used for measuring HSYNC
period. This output will pass composite sync signals and Macrovision signals if present on HSYNC
SOG
3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the
duration of the disruption of the normal HSYNC pattern. This is typically used for measuring VSYNC period.
Power supply for the analog section. Connect to a 3.3V supply and bypass each pin to GND
Ground return for V
Power supply for all digital I/Os. Connect to a 3.3V supply and bypass each pin to GND
Ground return for V
Power supply for crystal oscillator. Connect to a 3.3V supply and bypass to GND
Ground return for V
Bypass these pins to GND
3.3V input voltage for V
Regulated output voltage for V
and V
only supply power to V
Internal power for the ADC’s digital logic. Connect to VREG
with 0.1µF.
Internal power for the PLL’s digital logic. Connect to VREG
with 0.1µF.
Internal power for core logic. Connect to VREG
Reserved. Do not connect anything to these pins.
IN
CORE
.
and bypass at input pins as instructed below. Do not connect to anything else - this output can
A
D
X
.
, V
and V
OUT
PLL
CORE
CORE
, V
. This signal is usually not needed.
A
BYPASS
ISL98001
with 0.1µF. Do not connect these pins to each other or anything else.
COREADC
, V
voltage regulator. Connect to a 3.3V source and bypass to GND
PLL
COREADC
, V
.
COREADC
and V
, and V
CORE
DESCRIPTION
and V
OUT
PLL
.
and bypass each pin to GND
.
CORE
; typically 1.9V. Connect only to V
OUT
OUT
through a 10Ω resistor and bypass to GND
through a 10Ω resistor and bypass to GND
OUT
is generated 8 pixel clocks after
X
D
with 0.1µF.
with 0.1µF.
D
with 0.1µF.
PLL
A
D
with 0.1µF.
, V
with 0.1µF.
March 8, 2006
COREADC
IN
FN6148.3
or
D
D