FM6124 Ramtron Corporation, FM6124 Datasheet - Page 7

• Manufacturer Part Number: FM6124
• Description: Event Data Recorder With F-ram
• Manufacturer: Ramtron Corporation

To perform a selective read, the bus master sends out
the slave address with the LSB set to 0. This specifies
a write operation. According to the write protocol,
the bus master then sends the address bytes that are
loaded into the internal address latch. After the
FM6124 acknowledges the address, the bus master
issues a Start condition. This simultaneously aborts
the write operation and allows the read command to
be issued with the slave address LSB set to a 1. The
operation is now a read from the current address.
Read operations are illustrated below.
RTC/Companion Write Operation
All RTC and Companion writes operate in a similar
manner to memory writes. The distinction is that a
different device ID is used and only one byte address
is needed instead of two. Figure 10 illustrates a single
byte write to this device.
RTC/Companion Read Operation
As with writes, a read operation begins with the
Slave Address. To perform a register read, the bus
Rev. 4.0 (EOL)
July 2010
By FM6124
By Master
By FM6124
By Master
Start
S
Slave Address
Start
S
Address
F
Slave Address
IGURE
F
Acknowledge
IGURE
Address
1
7. C
A
8. S
URRENT
EQUENTIAL
Acknowledge
1
Data Byte
A
DDRESS
A
M
master supplies a Slave Address with the LSB set to
1. This indicates that a read operation is requested.
After receiving the complete Slave Address, the
FM6124 will begin shifting data out from the current
register address on the next clock. Auto-increment
operates for the special function registers as with the
memory address. A current address read for the
registers look exactly like the memory except that the
device ID is different.
The FM6124 contains two separate address registers,
one for the memory address and the other for the
register address. This allows the contents of one
address register to be modified without affecting the
current address of the other register. For example,
this would allow an interrupted read to the memory
while still providing fast access to an RTC register. A
subsequent memory read will then continue from the
memory address where it previously left off, without
requiring the load of a new memory address.
However, a write sequence always requires an
address to be supplied.
EMORY
M
Acknowledge
EMORY
Data Byte
Data
R
A
Data
EAD
R
EAD
Acknowledge
Data Byte
No
1
P
Acknowledge
No
1 P
Stop
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