FM6124 Ramtron Corporation, FM6124 Datasheet - Page 23

• Manufacturer Part Number: FM6124
• Description: Event Data Recorder With F-ram
• Manufacturer: Ramtron Corporation

Backup Power
The real-time clock and alarm are intended to be
permanently powered. When the primary system
power fails, the voltage on the VDD pin will drop.
When the VDD voltage is less than V
(and event counter) will switch to the backup power
supply on VBAK. The clock operates at extremely
low current in order to maximize battery or capacitor
life. However, an advantage of combining a clock
function with F-RAM memory is that data is not lost
regardless of the backup power source.
Trickle Charger
To facilitate capacitor backup, the VBAK pin can
optionally provide a trickle charge current. When the
VBC bit (register 18h bit 3) is set to a ‘1’, the V
pin will source approximately 80 µA until V
reaches V
without an external diode and resistor charger.
There is a Fast Charge mode which is enabled by the
FC bit (register 18h, bit 2). In this mode the trickle
charger current is set to approximately 1 mA,
allowing a large backup capacitor to charge more
quickly.
the VBC bit to 0 to prevent battery charging. The
VBAK circuitry includes an internal 1 K
resistor as a safety element.
Rev. 1.1
Dec. 2007
• In the case where no battery is used, the V
Note: systems using lithium batteries should clear
CF
pin should be tied to V
DD
. This charges the capacitor to V
Years
8 bits
32.768 kHz
crystal
SS
and VBC bit cleared.
F
Months
5 bits
IGURE
Ω
26. R
SW
series
, the RTC
EAL TIME
BAK
BAK
BAK
DD
6 bits
Date
User Registers
3 bits
Oscillator
/OSCEN
Days
C
LOCK
C
Calibration
When the CAL bit in register 00h is set to a ‘1’, the
clock enters calibration mode. The FM6124 devices
employ a digital method for calibrating the crystal
oscillator frequency. The digital calibration scheme
applies a digital correction to the RTC counters based
on the calibration settings, CALS and CAL.4-0. In
calibration mode (CAL=1), the ACS pin is driven
with a 512 Hz (nominal) square wave and the alarm
is temporarily unavailable. Any measured deviation
from 512 Hz translates into a timekeeping error. The
user measures the frequency and writes the
appropriate correction value to the calibration
register. The correction codes are listed in the table
below. For convenience, the table also shows the
frequency error in ppm. Positive ppm errors require a
negative adjustment that removes pulses. Negative
ppm errors require a positive correction that adds
pulses. Positive ppm adjustments have the CALS
(sign) bit set to 1, where as negative ppm adjustments
have CALS = 0. After calibration, the clock will have
a maximum error of ± 2.17 ppm or ± 0.09 minutes
per month at the calibrated temperature.
The user will not be able to see the effect of the
calibration setting on the 512 Hz output.
addition or subtraction of digital pulses occurs after
the 512 Hz output.
The calibration setting is stored in F-RAM so it is not
lost should the backup source fail. It is accessed with
bits CAL.4-0 in register 01h. This value only can be
written when the CAL bit is set to a 1. To exit the
calibration mode, the user must clear the CAL bit to a
ORE
B
Hours
6 bits
LOCK
D
Divider
Clock
IAGRAM
Minutes
7 bits
FM6124 Event Data Recorder
512 Hz or
SW out
1 Hz
Seconds
Update
Logic
7 bits
W
Page 23 of 28
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The