FM24C16-P Ramtron Corporation, FM24C16-P Datasheet
![no-image](/images/no-image-200.jpg)
FM24C16-P
Available stocks
Related parts for FM24C16-P
FM24C16-P Summary of contents
Page 1
... Industry Standard Configuration • Industrial Temperature -40° +85° C • 8-pin SOIC or DIP Pin Configuration caused by VSS Pin Names SDA SCL WP VSS VDD Ordering Information FM24C16-P FM24C16-S (800) 545-FRAM, (719) 481-7000, Fax (719) 481-7058 VDD SCL ...
Page 2
Counter SDA Serial to Parallel Converter SCL Control Logic WP Pin Description Pin Name I/O Pin Description SDA I/O Serial Data/Address: This is a bi-directional pin used to shift serial data and addresses for the two-wire interface. It employs an ...
Page 3
... This is explained in more detail in the interface section below. Users expect several obvious system benefits from the FM24C16 due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast write operation is less susceptible to corruption than an EEPROM since it is completed quickly ...
Page 4
... If the receiver acknowledges the last byte, this will cause the FM24C16 to attempt to drive the bus on the next clock while the master is sending a new command such as stop. ...
Page 5
... After all address information has been transmitted, data transfer between the bus master and the FM24C16 can begin. For a read operation the FM24C16 will place 8 data bits on the bus then wait for an acknowledge. If the acknowledge occurs, the next sequential byte will be transferred. If the acknowledge is not sent, the read operation is concluded ...
Page 6
... FM24C16 should read out the next sequential byte. There are four ways to properly terminate a read operation. Failing to properly terminate the read will most likely create a bus contention as the FM24C16 Rev. 2.1 Oct. 2002 Figure 5 Byte Write ...
Page 7
... By Master Address Start A S SLAVE ADDRESS 0 By FM24C16 Endurance Internally, a FRAM operates with a read and restore mechanism. Therefore, endurance cycles are applied for each read or write cycle. The FRAM architecture is based on an array of rows and columns. Rows are defined by A10-A3. Each access causes an endurance cycle for a row ...
Page 8
... When time to market is critical, FRAM can eliminate this simple obstacle. As soon as a write is issued to the FM24C16 effectively done -- no waiting. 5. RF/ID. In the area of contactless memory, FRAM provides an ideal solution. Since RF/ID memory is powered field, the long programming time and high current consumption needed to write EEPROM is unattractive ...
Page 9
Electrical Specifications Absolute Maximum Ratings Symbol V Power Supply Voltage with respect Voltage on any signal pin with respect Storage temperature STG T Lead temperature (Soldering, 10 seconds) LEAD Stresses above those ...
Page 10
AC Parameters (T = -40° 85° Symbol Parameter f SCL Clock Frequency SCL t Noise Suppression Time Constant on SP SCL, SDA t SCL Low to SDA Data Out Valid AA t Bus Free ...
Page 11
... FM24C16 from FM24C16 tHD:STA tHD:DAT tSU:DAT Valid Valid Data/Address bit 7 Data/Address bit 6 Start to FM24C16 to FM24C16 Min Units Notes 10 Years 1 tSP tSP tOF tLOW tSU:DAT tHD:DAT tDH Data bits Acknowledge 5-0 from FM24C16 to FM24C16 tAA Data/Address bit 5-0 Acknowledge to FM24C16 from FM24C16 ...
Page 12
SOIC (JEDEC Standard MS-012 variation AA) Index Area Pin Selected Dimensions Refer to JEDEC MS-012 for complete dimensions and notes. Controlling dimensions in millimeters. Conversions to inches are not exact. Symbol Dim A mm ...
Page 13
DIP JEDEC MS-001 Index Area A1 D1 Selected Dimensions Refer to JEDEC MS-001 for complete dimensions and notes. Controlling dimensions in inches. Conversions to millimeters are not exact. Symbol Dim in. mm ...