FM6124 Ramtron Corporation, FM6124 Datasheet - Page 20

• Manufacturer Part Number: FM6124
• Description: Event Data Recorder With F-ram
• Manufacturer: Ramtron Corporation

Manual Reset
The RSTB is a bi-directional signal allowing the FM6124
to filter and de-bounce a manual reset switch. The RSTB
input detects an external low condition and responds by
driving the RSTB signal low for 100 ms (max.). This
effectively filters and de-bounces a reset switch. After this
timeout (t
RSTB pin, but I
Note the internal weak pull-up eliminates the need for
additional external components.
Reset Flags
In case of a reset condition, a flag bit will be set to indicate
the source of the reset. A low-V
POR bit, register 09h bit 5. There are two watchdog reset
flags - one for an early fault (EWDF) and the other for a
late fault (LWDF), located in register 09h bits 7 and 6. A
manual reset will result in no flag being set, so the absence
of a flag is a manual reset. Note that the bits are set in
response to reset sources but they must be cleared by the
user. It is possible to read the register and have both
sources indicated if both have occurred since the user
cleared them.
Power Fail Comparator
An analog comparator compares the PFI input pin to an
onboard 1.5V reference. When the PFI input voltage drops
below this threshold, the comparator will drive the PFO
pin to a low state. The comparator has 100 mV of
hysteresis (rising voltage only) to reduce noise sensitivity.
The most common application of this comparator is to
create an early warning power fail interrupt (NMI). This
can be accomplished by connecting the PFI pin to an
upstream power supply via a resistor divider. An
application circuit is shown below. The comparator is a
general purpose device and its application is not limited to
the NMI function.
Rev. 4.0 (EOL)
July 2010
Behavior
Switch
RSTB
RPW
MCU
), the user may continue pulling down on the
Switch
Reset
2
C commands will not be locked out.
F
IGURE
FM6124
drives
23. M
RSTB
100 ms (max.)
ANUAL RESET
DD
FM6124
reset is indicated by the
If the power-fail comparator is not used, the PFI pin should
be tied to either V
drive to V
Event Counter
The FM6124 offers the user a nonvolatile 16-bit event
counter. The input pin CNT has a programmable edge
detector. The CNT pin clocks the counter. The counter is
located in registers 0E-0Fh. When the programmed edge
polarity occurs, the counter will increment its count value.
The register value is read by setting the RC bit (register
0Dh, bit 3) to 1. This takes a snapshot of the counter byte
allowing a stable value even if a count occurs during the
read. The register value can be written by first setting the
WC bit (register 0Dh, bit 2) to 1. The user then may clear
or preset the counter by writing to registers 0E-0Fh.
Counts are blocked when the WC bit is set, so the user
must clear the bit to allow counts.
The counter polarity control bit is CP, register 0Dh bit 0.
When CP is 0, the counter increments on a falling edge of
CNT, and when CP is set to 1, the counter increments on a
rising edge of CNT. The polarity bit CP is nonvolatile.
The counter does not wrap back to zero when it reaches the
limit of 65,535 (FFFFh). Care must be taken prior to the
rollover, and a subsequent counter reset operation must
occur to continue counting.
There is also a control bit that allows the user to define the
counter as nonvolatile or battery-backed. The counter is
nonvolatile when the NVC bit (register 0Dh, bit 7) is logic
1 and battery-backed when the NVC bit is logic 0. Setting
CNT
NMI input
To MCU
F
IGURE
DD
PFO
23. C
or V
CP
F
SS
IGURE
OMPARATOR AS
DD
as well.
or V
FM6124
+
-
24. E
1.5V ref
SS
. Note that the PFO output will
VENT COUNTER
P
OWER
Regulator
16-bit Counter
Page 20 of 53
F
AIL
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VDD
ARNING