FM6124 Ramtron Corporation, FM6124 Datasheet - Page 31

• Manufacturer Part Number: FM6124
• Description: Event Data Recorder With F-ram
• Manufacturer: Ramtron Corporation

Rev. 4.0 (EOL)
July 2010
0x17
0x16
0x15
0x14
0x13
0x12
0x11
0x10
0x0F
0x0E
0x0D
NVC
RC
WC
POLL
CP
Serial Number Byte 7
Serial Number Byte 6
Serial Number Byte 5
Serial Number Byte 4
Serial Number Byte 3
Serial Number Byte 2
Serial Number Byte 1
Serial Number Byte 0
All serial number bytes are read/write when SNL=0, read-only when SNL=1. Nonvolatile.
Event Counter Byte 1
Event Counter Byte 1. Increments on programmed edge event on CNT input. Nonvolatile when NVC=1,
Battery-backed when NVC=0, read/write.
Event Counter Byte 0
Event Counter Byte 0. Increments on programmed edge event on CNT input. Nonvolatile when NVC=1,
Battery-backed when NVC=0, read/write.
Event Counter Control
Nonvolatile/Volatile Counter: Setting this bit to 1 makes the counter nonvolatile and counter operates only when
V
V
Read Counter. Setting this bit to 1 takes a snapshot of the two counter bytes allowing the system to read the
values without missing count events. The RC bit will be automatically cleared.
Write Counter. Setting this bit to a 1 allows the user to write the counter bytes. While WC=1, the counter is
blocked from count events on the CNT pin. The WC bit must be cleared by the user to activate the counter.
Polled Mode: When POLL=1, the CNT pin is sampled for 30µs every 125ms. If POLL is set, the NVC bit is
internally cleared and the CP bit is set to detect a rising edge. The RTC oscillator must be enabled (/OSCEN=0)
to operate in polled mode. When POLL=0, CNT pin is continuously active. Nonvolatile, read/write.
The CNT pin detects falling edges when CP = 0, rising edges when CP = 1. Nonvolatile, read/write.
DD
BAK
SN.63
SN.55
SN.47
SN.39
SN.31
SN.23
SN.15
EC.15
NVC
SN.7
EC.7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
D7
is greater than V
or V
DD
power. Nonvolatile, read/write.
SN.62
SN.54
SN.46
SN.38
SN.30
SN.22
SN.14
EC.14
SN.6
EC.6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
-
TP
. Setting this bit to 0 makes the counter volatile, which allows counter operation under
SN.61
SN.53
SN.45
SN.37
SN.29
SN.21
SN.13
EC.13
SN.5
EC.5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
-
SN.60
SN.52
SN.44
SN.36
SN.28
SN.20
SN.12
EC.12
SN.4
EC.4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
-
SN.59
SN.51
SN.43
SN.35
SN.27
SN.19
SN.11
EC.11
SN.3
EC.3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
RC
SN.58
SN.50
SN.42
SN.34
SN.26
SN.18
SN.10
EC.10
SN.2
EC.2
WC
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
FM6124 Event Data Recorder
SN.57
SN.49
SN.41
SN.33
SN.25
SN.17
POLL
SN.9
SN.1
EC.9
EC.1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
Page 31 of 53
SN.56
SN.48
SN.40
SN.32
SN.24
SN.16
SN.8
SN.0
EC.8
EC.0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
CP