FM6124 Ramtron Corporation, FM6124 Datasheet - Page 32

• Manufacturer Part Number: FM6124
• Description: Event Data Recorder With F-ram
• Manufacturer: Ramtron Corporation

Rev. 4.0 (EOL)
July 2010
0x0C
WDE
WDET(4:0) Watchdog EndTime: Sets the ending time for the watchdog window timer with 60 ms (min.) resolution. The
0x0B
WDST(4:0) Watchdog StartTime. Sets the starting time for the watchdog window timer with 25 ms (max.) resolution. The
0x0A
WR(3:0)
Watchdog Control
Watchdog Enable: When WDE=1, a watchdog timer fault will cause the RSTB signal to go active. When WDE
= 0 the timer runs but has no effect on the RSTB pin. Nonvolatile, read/write.
window timer allow independent leading and trailing edges (start and end of window) to be set. New watchdog
timeouts are loaded when the timer is restarted by writing the 1010b pattern to WR(3:0). To save power (disable
timer circuit), the EndTime may be set to all zeroes. Nonvolatile, read/write.
Watchdog Control
window timer allow independent leading and trailing edges (start and end of window) to be set. New watchdog
timer settings are loaded when the timer is restarted by writing the 1010b pattern to WR(3:0). Nonvolatile,
read/write.
Watchdog Restart
Watchdog Restart. Writing a pattern 1010b to WR(3:0) restarts the watchdog timer. The upper nibble contents
do not affect this operation. Writing any pattern other than 1010b to WR3-0 has no effect on the watchdog.
Write-only.
WDE
D7
D7
D7
-
-
Watchdog EndTime
Disables Timer
Watchdog StartTime
0 ms (default)
157.5 ms
232.5 ms
217.5 ms
1200 ms
1260 ms
1320 ms
1740 ms
1800 ms
1860 ms
15.0 ms
22.5 ms
150 ms
165 ms
(min.)
(min.)
225 ms
120 ms
180 ms
7.5 ms
60 ms
.
.
.
.
.
.
.
.
.
.
.
.
D6
D6
D6
-
-
-
4000 ms
4200 ms
4400 ms
5800 ms
6000 ms
6200 ms
525 ms
500 ms
550 ms
725 ms
750 ms
775 ms
(max.)
400 ms
600 ms
50 ms
200 ms
25 ms
75 ms
(max.)
D5
D5
D5
-
-
-
.
.
.
.
.
.
.
.
.
.
.
.
WDET4 WDET3 WDET2 WDET1 WDET0
WDST4 WDST3 WDST2 WDST1 WDST0
WDET4
WDST4
D4
D4
D4
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
-
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
1
WDET3
WDST3
WR3
D3
D3
D3
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
WDET2
WDST2
0
0
1
1
0
0
1
0
1
1
0
0
1
1
0
0
1
0
1
1
WR2
D2
D2
D2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
FM6124 Event Data Recorder
WDET1
WDST1
WR1
D1
D1
D1
WDET0
WDST0
Page 32 of 53
WR0
D0
D0
D0