PIC16F627-04 Microchip Technology, PIC16F627-04 Datasheet - Page 72

• Manufacturer Part Number: PIC16F627-04
• Description: FLASH-Based 8-Bit CMOS Microcontrollers
• Manufacturer: Microchip Technology

PIC16F62X
REGISTER 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
DS40300B-page 72
bit7
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
R/W-0
SPEN
SPEN: Serial Port Enable bit
(Configures RB1/RX/DT and RB2/TX/CK pins as serial port pins when bits TRISB<2:17> are set)
1 = Serial port enabled
0 = Serial port disabled
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Synchronous mode - master:
Synchronous mode - slave:
CREN: Continuous Receive Enable bit
Asynchronous mode:
Synchronous mode:
ADEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
Asynchronous mode 8-bit (RX9=0):
FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
RX9D: 9th bit of received data (Can be parity bit)
R/W-0
Don’t care
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Unused in this mode
1 = Enables continuous receive
0 = Disables continuous receive
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
1 = Enables address detection, enable interrupt and load of the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit
Unused in this mode
Synchronous mode
Unused in this mode
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
ADEN
Preliminary
FERR
R-0
OERR
R-0
bit0
RX9D
R-x
R = Readable bit
W = Writable bit
U = Unimplemented bit,
-n = Value at POR reset
x = unknown
1999 Microchip Technology Inc.
read as ’0’