PIC16F627-04 Microchip Technology, PIC16F627-04 Datasheet - Page 108

• Manufacturer Part Number: PIC16F627-04
• Description: FLASH-Based 8-Bit CMOS Microcontrollers
• Manufacturer: Microchip Technology

PIC16F62X
14.6.1
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION<6>) is set, or fall-
ing, if INTEDG bit is clear. When a valid edge appears
on the RB0/INT pin, the INTF bit (INTCON<1>) is set.
This interrupt can be disabled by clearing the INTE
control bit (INTCON<4>). The INTF bit must be cleared
in software in the interrupt service routine before
re-enabling this interrupt. The RB0/INT interrupt can
wake-up the processor from SLEEP, if the INTE bit was
set prior to going into SLEEP. The status of the GIE bit
decides whether or not the processor branches to the
interrupt vector following wake-up. See Section 14.9 for
details on SLEEP and Figure 14-19 for timing of
wake-up from SLEEP through RB0/INT interrupt.
14.6.2
An overflow (FFh
set the T0IF (INTCON<2>) bit. The interrupt can
be
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 6.0.
FIGURE 14-17: INT PIN INTERRUPT TIMING
TABLE 14-8:
DS40300B-page 108
Address Name
Note 1: INTF flag is sampled here (every Q1).
INSTRUCTION FLOW
0Ch
8Ch
0Bh
GIE bit
(INTCON<7>)
Note 1:
INTF flag
(INTCON<1>)
CLKOUT
INT pin
OSC1
Instruction
executed
Instruction
fetched
PC
enabled/disabled
2: Asynchronous interrupt latency = 3-4 Tcy. Synchronous latency = 3 Tcy, where Tcy = instruction cycle time. Latency
3: CLKOUT is available only in ER oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
RB0/INT INTERRUPT
TMR0 INTERRUPT
INTCON
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
PIR1
PIE1
Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during normal operation.
3
SUMMARY OF INTERRUPT REGISTERS
Q1
Bit 7
EEIF
EEIE
Inst (PC-1)
GIE
Inst (PC)
00h) in the TMR0 register will
1
Q2
PC
by
Q3
4
CMIF
CMIE
PEIE
Bit 6
setting/clearing
Q4
5
Q1
RCIF
RCIE
Bit 5
T0IE
Inst (PC+1)
Inst (PC)
Q2
1
PC+1
Q3
INTE
Bit 4
TXIF
TXIE
T0IE
Preliminary
Q4
Bit 3
RBIE
Interrupt Latency
Q1
—
—
Dummy Cycle
Q2
14.6.3
An input change on PORTB <7:4> sets the RBIF
(INTCON<0>) bit. The interrupt can be enabled/dis-
abled by setting/clearing the RBIE (INTCON<4>) bit.
For operation of PORTB (Section 5.2).
14.6.4
See Section 9.6 for complete description of comparator
interrupts.
PC+1
—
CCP1IF
CCP1IE
Note:
Bit 2
T0IF
Q3
PORTB INTERRUPT
COMPARATOR INTERRUPT
Q4
2
TMR2IF
TMR2IE
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
Bit 1
INTF
Q1
Dummy Cycle
Inst (0004h)
Q2
TMR1IF
TMR1IE
0004h
Bit 0
RBIF
Q3
1999 Microchip Technology Inc.
Value on POR
Q4
0000 000x
0000 -000
0000 -000
Reset
Q1
Inst (0005h)
Q2
Inst (0004h)
0005h
other resets
Value on all
0000 000u
0000 -000
0000 -000
Q3
Q4
(1)