PIC16F627-04 Microchip Technology, PIC16F627-04 Datasheet - Page 65

• Manufacturer Part Number: PIC16F627-04
• Description: FLASH-Based 8-Bit CMOS Microcontrollers
• Manufacturer: Microchip Technology

10.2
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RB3/CCP1 pin is:
• driven High
• driven Low
• remains Unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 10-2: COMPARE MODE
TABLE 10-2
0Bh/8Bh/1
0Bh/18Bh
0Ch
8Ch
87h
0Eh
0Fh
10h
15h
16h
17h
Legend:
RB3/CCP1
Pin
Address
1999 Microchip Technology Inc.
Special event trigger will reset Timer1, but not
set interrupt flag bit TMR1IF (PIR1<0>)
Output Enable
TRISB<3>
Compare Mode
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1.
CCP1CON
CCPR1H
CCPR1L
INTCON
TMR1H
T1CON
TMR1L
TRISB
Name
PIR1
PIE1
Q
Special Event Trigger (CCP2 only)
OPERATION BLOCK
DIAGRAM
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
R
S
CCP1CON<3:0>
Mode Select
Output
Logic
PORTB Data Direction Register
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1register
Capture/Compare/PWM register1 (LSB)
Capture/Compare/PWM register1 (MSB)
EEIE
Bit 7
EEIF
GIE
—
—
(PIR1<2>)
Set flag bit CCP1IF
match
CMIF
CMIF
Bit 6
PEIE
—
—
CCPR1H CCPR1L
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
TMR1H
CCP1X
Comparator
RCIF
RCIE
Bit 5
T0IE
TMR1L
CCP1Y
INTE
TXIF
TXIE
Bit 4
Preliminary
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
RBIE
Bit 3
—
—
10.2.1
The user must configure the RB3/CCP1 pin as an out-
put by clearing the TRISB<3> bit.
10.2.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
10.2.3
When generate software interrupt is chosen the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
10.2.4
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
Note:
CCP1IF
CCP1IE TMR2IE
Bit 2
T0IF
CCP PIN CONFIGURATION
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
Clearing the CCP1CON register will force
the RB3/CCP1 compare output latch to the
default low level. This is not the data latch.
TMR2IF
INTF
Bit 1
TMR1IF 0000 -000 0000 -000
TMR1IE 0000 -000 0000 -000
PIC16F62X
RBIF
Bit 0
0000 000x 0000 000u
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Value on
DS40300B-page 65
POR
Value on
all other
resets