PIC16F627-04 Microchip Technology, PIC16F627-04 Datasheet
PIC16F627-04
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PIC16F627-04 Summary of contents
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... Serial in-circuit programming (via two pins) • Four user programmable ID locations CMOS Technology: • Low-power, high-speed CMOS FLASH technology • Fully static design • Wide operating voltage range - PIC16F627 - 3.0V to 5.5V - PIC16F628 - 3.0V to 5.5V - PIC16LF627 - 2.0V to 5.5V - PIC16LF628 - 2.0V to 5.5V • Commercial, industrial and extended temperature range • Low power consumption - < ...
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... RA4/TOCKI/CMP2 3 RA5/MCLR/THV RB0/INT 8 RB1/RX/DT 9 RB2/TX/CK 10 RB3/CCP1 Device Differences Device PIC16F627 PIC16F628 PIC16LF627 PIC16LF628 Note 1: If you change from this device to another device, please verify oscillator characteristics in your application. DS40300B-page 2 RA1/AN1 18 RA0/AN0 17 RA7/OSC1/CLKIN 16 15 RA6/OSC2/CLKOUT RB7/T1OSI 12 ...
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... However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: • Fill out and mail in the reader response form in the back of this data sheet. • E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document. 1999 Microchip Technology Inc. To Our Valued Customers Preliminary PIC16F62X DS40300B-page 3 ...
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... PIC16F62X NOTES: DS40300B-page 4 Preliminary 1999 Microchip Technology Inc. ...
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... I/O flex- ibility make the PIC16F62X very versatile. 1999 Microchip Technology Inc. 1.1 Development Support The PIC16F62X family is supported by a full-featured macro assembler, a software simulator, an in-circuit of low-cost, ...
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... Brown-out Detect Packages ® All PICmicro Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16F62X Family devices use serial programming with clock pin RB6 and data pin RB7. DS40300B-page 6 PIC16F627 PIC16F628 2048 1024 ...
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... The devices are standard FLASH devices but with all program locations and configuration options already programmed by the factory. Certain code and prototype verification procedures production shipments are available. Please contact your Microchip Technology sales office for more details. 2.3 Serialized Quick-Turnaround-Production (SQTP ) Devices SM ...
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... PIC16F62X NOTES: DS40300B-page 8 Preliminary 1999 Microchip Technology Inc. ...
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... MHz) except for program branches. The Table below lists program memory (Flash, Data and EEPROM). Memory Device FLASH RAM Program Data PIC16F627 1024 x 14 224 x 8 PIC16F628 2048 x 14 224 x 8 PIC16LF627 1024 x 14 224 x 8 PIC16LF628 ...
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... OSC2/CLKOUT MCLR Timer0 Comparator CCP1 V REF Memory Device FLASH RAM Program Data PIC16F627 1024 x 14 224 x 8 PIC16F628 2048 x 14 224 x 8 PIC16LF627 1024 x 14 224 x 8 PIC16LF628 2048 x 14 224 x 8 Note 1: Higher order bits are from the STATUS register. ...
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... Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode. Note 3: This buffer is a Schmitt Trigger I/O when used in USART/Synchronous mode. Note 4: This buffer is a Schmitt Trigger I/O when used in CCP mode. Note 5: This buffer is a Schmitt Trigger input when used in low voltage program mode. 1999 Microchip Technology Inc. I/O/P Buffer Type ...
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... Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write PC+1 Fetch INST (PC+1) Execute INST (PC) Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Preliminary Internal phase clock PC+2 Fetch INST (PC+2) Execute INST (PC+1) Flush Fetch SUB_1 Execute SUB_1 1999 Microchip Technology Inc. ...
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... Program Memory Organization The PIC16F62X has a 13-bit program counter capable of addressing program memory space. Only the first (0000h - 03FFh) for the PIC16F627 and (0000h - 07FFh) for the PIC16F628 are physically implemented. Accessing a location above these boundaries will cause a wrap-around within the first space (PIC16F627 space (PIC16F628) ...
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... PIC16F62X FIGURE 4-3: DATA MEMORY MAP OF THE PIC16F627 AND PIC16F628 Indirect addr.(*) Indirect addr.(*) 00h 01h TMR0 02h PCL STATUS 03h FSR 04h 05h PORTA 06h PORTB 07h 08h 09h PCLATH 0Ah INTCON 0Bh 0Ch PIR1 0Dh TMR1L 0Eh TMR1H 0Fh 10h ...
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... Note 1: Other (non power-up) resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation. 1999 Microchip Technology Inc. The special registers can be classified into two sets (core and peripheral). The special function registers associated with the “core” functions are described in this section ...
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... TX9D 0000 -010 0000 -010 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu RD ---- x000 ---- q000 -------- -------- — — VR0 000- 0000 000- 0000 1999 Microchip Technology Inc. ...
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... Legend: — = Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: Other (non power-up) resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation. 1999 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ...
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... PS0 1111 1111 1111 1111 0000 0000 0000 0000 C 0001 1xxx 000q quuu xxxx xxxx uuuu uuuu — — TRISB0 1111 1111 1111 1111 — — — — — — ---0 0000 ---0 0000 RBIF 0000 000x 0000 000u 1999 Microchip Technology Inc. ...
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... Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. 1999 Microchip Technology Inc recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect any status bit ...
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... DS40300B-page 20 Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT (PSA = 1). See Section 6.3.1 R/W-1 R/W-1 R/W-1 R/W-1 PSA PS2 PS1 PS0 bit0 128 Preliminary R = Readable bit W = Writable bit -n = Value at POR reset 1999 Microchip Technology Inc. ...
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... RBIF: RB Port Change Interrupt Flag bit 1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software None of the RB7:RB4 pins have changed state 1999 Microchip Technology Inc. Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...
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... Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt DS40300B-page 22 U R/W-0 R/W-0 R/W-0 - CCP1IE TMR2IE TMR1IE bit0 Preliminary R = Readable bit W = Writable bit U = Unimplemented bit, read as ’0’ Value at POR reset 1999 Microchip Technology Inc. ...
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... TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software TMR1 register did not overflow 1999 Microchip Technology Inc. Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...
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... Note 1: When in ER oscillator mode, setting OSCF = 1 will cause the oscillator speed to change to the speed specified by the external resistor. DS40300B-page 24 has in the R/W-1 U-0 R/W-q R/W-q OSCF — POR BOD bit0 Preliminary R = Readable bit W = Writable bit U = Unimplemented bit, read as ’0’ Value at POR reset 1999 Microchip Technology Inc. ...
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... GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the application note “Implementing a Table Read" (AN556). 1999 Microchip Technology Inc. 4.3.2 STACK The PIC16F62X family has an 8 level deep x 13-bit wide hardware stack (Figure 4-1 and Figure 4-2) ...
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... Bank 1 Bank 2 Bank 3 Preliminary INDIRECT ADDRESSING 0x20 ;initialize pointer FSR ;to RAM INDF ;clear INDF register FSR ;inc pointer FSR,4 ;all done? NEXT ;no clear next ;yes continue Indirect Addressing 7 0 FSR register location select 1999 Microchip Technology Inc. ...
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... VRCON (voltage reference control register) register. When selected as a comparator input, these pins will read as ’0’s. 1999 Microchip Technology Inc. PIC16F62X Note 1: On reset, the TRISA register is set to all inputs. The digital inputs are disabled and ...
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... Data Bus PORTA CK Q Data Latch D Q I/O Pin WR TRISA TRIS Latch RD TRISA RD PORTA To Comparator V ROE V REF Preliminary PIN REF RA2 Pin Analog Input Mode Schmitt Trigger Input Buffer 1999 Microchip Technology Inc. ...
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... BLOCK DIAGRAM OF RA4/T0CKI PIN Data Bus D Q Comparator Output WR PORTA CK Q Data Latch TRISA CK Q TRIS Latch RD TRISA RD PORTA TMR0 Clock Input 1999 Microchip Technology Inc. Comparator Mode = 110 1 0 Input Mode Comparator Mode = 110 Preliminary PIC16F62X ...
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... FIGURE 5-5: BLOCK DIAGRAM OF THE RA5/MCLR/THV PIN MCLR circuit Program mode Data D Q Bus PORT Data Latch TRIS CK Q TRIS Latch RD TRIS RD Port DS40300B-page 30 MCLRE MCLR Filter(1) HV Detect Preliminary V DD RA5/MCLR/THV V SS 1999 Microchip Technology Inc. ...
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... Bus PORTA Data Latch TRISA CK Q TRIS Latch (Fosc=100, 101, 110, 111) RD TRISA Q RD PORTA CLKOUT is 1/4 of the Fosc frequency. 1999 Microchip Technology Inc. From OSC1 Oscillator Circuit (Fosc=110, 100 Preliminary PIC16F62X V DD RA6/OSC2/CLKOUT Pin ...
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... Bus PORTA Data Latch TRISA CK Q TRIS Latch (Fosc=101, 100) RD TRISA PORTA DS40300B-page 32 To OSC2 Oscillator Circuit CLKIN to core Schmitt Trigger (Fosc=101, 100) D Preliminary V DD RA7/OSC1/CLKIN Pin V SS Schmitt Trigger Input Buffer 1999 Microchip Technology Inc. ...
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... VRCON VREN VROE Legend: — = Unimplemented locations, read as ‘0’ unchanged unknown Note: Shaded bits are not used by PORTA. 1999 Microchip Technology Inc. Function Bi-directional I/O port/comparator input Bi-directional I/O port/comparator input Bi-directional I/O port/analog/comparator input or V Bi-directional I/O port/analog/comparator input/comparator output Bi-directional I/O port/external clock input for TMR0 or comparator output. ...
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... The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature. Preliminary 1999 Microchip Technology Inc. ...
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... FIGURE 5-8: BLOCK DIAGRAM OF RB0/INT PIN Data Bus PORTB CK Data Latch TRISB CK TRIS Latch RD TRISB RD PORTB INT input 1999 Microchip Technology Inc. RBPU TTL input buffer Preliminary PIC16F62X weak P pull-up RB0/INT pin V SS Schmitt Trigger Buffer ...
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... Note 1: Port/Peripheral select signal selects between port data and peripheral output. Note 2: Peripheral OE( output enable) is only active if peripheral select is active. DS40300B-page 36 RBPU Schmitt Trigger Preliminary V DD weak pull- RB1/RX/DT pin TTL input buffer RD PORTB 1999 Microchip Technology Inc. ...
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... Data Latch D WR TRISB TRIS Latch RD TRISB (2) Peripheral OE RD PORTB USART Slave Clock in Note 1: Port/Peripheral select signal selects between port data and peripheral output. Note 2: Peripheral OE( output enable) is only active if peripheral select is active. 1999 Microchip Technology Inc. RBPU ...
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... TRIS Latch RD TRISB RD PORTB CCP input Note 1: Peripheral Select is defined by CCP1M3:CCP1M0. (CCP1CON<3:0>) DS40300B-page 38 RBPU Schmitt Trigger Preliminary weak pull- RB3/CCP1 pin Vss TTL input buffer PORTB 1999 Microchip Technology Inc. ...
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... FIGURE 5-12: BLOCK DIAGRAM OF RB4/PGM PIN Data Bus WR PORTB Data Latch WR TRISB TRIS Latch RD TRISB LVP RD PORTB PGM input Note: The low voltage programming disables the interrupt on change and the weak pullups on RB4. 1999 Microchip Technology Inc. RBPU Schmitt Trigger ...
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... FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN Data Bus PORTB CK Data Latch TRISB CK TRIS Latch RD TRISB RD PORTB Set RBIF From other RB<7:4> pins DS40300B-page 40 RBPU TTL input buffer Port EN Q3 Preliminary 1999 Microchip Technology Inc weak P pull-up RB5 pin V SS ...
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... FIGURE 5-14: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI PIN Data Bus WR PORTB Data Latch WR TRISB TRIS Latch RD TRISB T1OSCEN RD PORTB TMR1 Clock From RB7 Serial programming clock 1999 Microchip Technology Inc. RBPU Schmitt Trigger Set RBIF From other RB<7:4> pins Preliminary PIC16F62X ...
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... Serial programming input Set RBIF DS40300B-page weak pull- RB6 T1OSCEN Schmitt Trigger From other Q D RB<7:4> pins EN Preliminary TMR1 oscillator RB7/T1OSI pin Vss TTL input buffer Q1 RD Port Q3 1999 Microchip Technology Inc. ...
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... RBPU INTEDG Legend unchanged unknown Note: Shaded bits are not used by PORTB. 1999 Microchip Technology Inc. Function Bi-directional I/O port/external interrupt. Can be software programmed for internal weak pull-up. Bi-directional I/O port/ USART receive pin/synchronous data I/O. Can be software programmed for internal weak pull-up. Bi-directional I/O port/ USART transmit pin/synchronous clock I/O. Can be software programmed for internal weak pull-up ...
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... This example shows write to PORTB followed by a read from PORTB. Note that: data setup time = (0. where T = instruction cycle and CY TPD = propagation delay of Q1 cycle to output valid. Therefore, at higher clock frequencies, a write followed by a read may be problematic. 1999 Microchip Technology Inc. ...
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... Fetch T0 T0+1 TMR0 Instruction Executed 1999 Microchip Technology Inc. bit (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2. The prescaler is shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by the control bit PSA (OPTION< ...
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... PC +1 Inst (PC+1) Dummy cycle Inst (PC) , where T = instruction cycle time. CY Preliminary PC+4 PC+5 PC+6 MOVF TMR0,W NT0+1 Read TMR0 Read TMR0 reads NT0 reads NT0 + 01h 02h 0004h 0005h Inst (0004h) Inst (0005h) Dummy cycle Inst (0004h) 1999 Microchip Technology Inc. ...
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... External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. 1999 Microchip Technology Inc. When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling ...
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... Watchdog Timer. The prescaler is not readable or writable SYNC Cycles PSA 8-bit Prescaler 8 8-to-1MUX PS0 - PS2 PSA WDT Time-out Preliminary TMR0 register (e.g., CLRF 1, Data Bus 8 TMR0 reg Set flag bit T0IF on Overflow 1999 Microchip Technology Inc. ...
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... Legend: — = Unimplemented locations, read as ‘0’ unchanged unknown Note: Shaded bits are not used by TMR0 module. 1999 Microchip Technology Inc. To change prescaler from the WDT to the TMR0 module use the sequence shown in Example 6-2. This precaution must be taken even if the WDT is disabled. ...
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... Timer1 also has an internal “reset input”. This reset can be generated by the CCP module (Section 10.0). Register 7-1 shows the Timer1 control register. For the PIC16F627 and PIC16F628, when the Timer1 oscillator is enabled (T1OSCEN is set), the RB7/T1OSI and RB6/T1OSO/T1CKI pins become inputs. That is, the TRISB< ...
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... T1OSC RB6/T1OSO/T1CKI RB7/T1OSI Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. 1999 Microchip Technology Inc. internal phase clock (Tosc) synchronization. Also, there is a delay in the actual incrementing of TMR1 after syn- chronization. ...
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... The user must provide a software time delay to ensure proper oscillator start-up. TABLE 7-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Osc Type Freq LP 32 kHz 100 kHz 200 kHz These values are for design guidance only. Preliminary 1999 Microchip Technology Inc ...
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... T1CON — — Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by the Timer1 module. 1999 Microchip Technology Inc. 7.6 Resetting of Timer1 Register Pair (TMR1H, TMR1L) TMR1H and TMR1L registers are not reset to 00h on a POR or any other reset except by the CCP1 special event triggers ...
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... FIGURE 8-1: Sets flag TMR2 bit TMR2IF output Reset Postscaler 1:1 to 1:16 4 Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock. Preliminary TIMER2 BLOCK DIAGRAM (1) Prescaler TMR2 reg F /4 OSC 1:1, 1:4, 1:16 2 Comparator EQ PR2 reg 1999 Microchip Technology Inc. ...
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... TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 12h T2CON — 92h PR2 Timer2 Period Register Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by the Timer2 module. 1999 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 R/W-0 bit0 Bit 5 Bit 4 Bit 3 ...
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... PIC16F62X NOTES: DS40300B-page 56 Preliminary 1999 Microchip Technology Inc. ...
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... C2 V – connects to RA1 IN bit 2-0: CM2:CM0: Comparator mode Figure 9-1 shows the comparator modes and CM2:CM0 bit settings. 1999 Microchip Technology Inc. The CMCON register, shown in Register 9-1, controls the comparator input and output multiplexers. A block two analog diagram of the comparator is shown in Figure 9-1. ...
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... Off (Read as ’0’) C1 Vin+ Vin- Off (Read as ’0’) C2 Vin+ CIS = 0 Vin- CIS = 1 C1OUT C1 Vin+ CIS = 0 Vin- CIS = 1 C2OUT C2 Vin+ From Vref Module Vin- C1OUT C1 Vin+ Vin- C2OUT C2 Vin+ CIS = 0 Vin- CIS = 1 C1OUT C1 Vin+ Vin- C2OUT C2 Vin+ 1999 Microchip Technology Inc. ...
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... The shaded areas of the output of the comparator in Figure 9-2 represent the uncertainty due to input offsets and response time. 1999 Microchip Technology Inc. 9.3 Comparator Reference An external or internal reference signal may be used depending on the comparator operating mode. The ...
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... Schmitt Trigger input specification. 2: Analog levels on any pin that is defined as a digital input may cause the input buffer to consume more current than is specified. Port Pins MULTIPLEX CMCON EN CL NRESET Preliminary 1999 Microchip Technology Inc. CnINV ...
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... LEAKAGE 1999 Microchip Technology Inc. wake up the device from SLEEP mode when enabled. While the comparator is powered-up, higher sleep currents than shown in the power down current specification will occur. Each comparator that is operational will consume additional current as shown in the comparator specifications. To minimize power consumption while in SLEEP mode, turn off the comparators, CM< ...
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... CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 11-1 1111 11-1 1111 Preliminary Value on Value on Bit 0 All Other POR Resets CM0 0000 0000 0000 0000 VR0 000- 0000 000- 0000 RBIF 0000 000x 0000 000u 1999 Microchip Technology Inc. ...
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... Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 11xx = PWM mode 1999 Microchip Technology Inc. Additional information on the CCP module is available in the PICmicro™ Mid-Range Reference Manual, (DS33023) ...
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... EXAMPLE 10-1: CHANGING BETWEEN CLRF CCP1CON MOVLW NEW_CAPT_PS MOVWF CCP1CON CCPR1L TMR1L Preliminary Example 10-1 shows the recom- CAPTURE PRESCALERS ;Turn CCP module off ;Load the W reg with ; the new prescaler ; mode value and CCP ON ;Load CCP1CON with this ; value 1999 Microchip Technology Inc. ...
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... CCP1CON — — Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by Capture and Timer1. 1999 Microchip Technology Inc. 10.2.1 CCP PIN CONFIGURATION The user must configure the RB3/CCP1 pin as an out- put by clearing the TRISB<3> bit. Note: Clearing the CCP1CON register will force the RB3/CCP1 compare output latch to the default low level ...
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... PWM period the CCP1 pin will not be cleared. For an example PWM period and duty cycle calcula- tion, see the PICmicro™ Mid-Range Reference Manual (DS33023). Preliminary • OSC (TMR2 prescale value) Section 8.0) is Tosc • (TMR2 prescale value) Fosc ( ) log Fpwm bits log (2) 1999 Microchip Technology Inc. ...
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... CCPR1L CCPR1H Capture/Compare/PWM register1 (MSB) 16h 17h CCP1CON — — Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by PWM and Timer2. 1999 Microchip Technology Inc. 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 0xFF 0xFF 0xFF 10 10 ...
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... PIC16F62X NOTES: DS40300B-page 68 Preliminary 1999 Microchip Technology Inc. ...
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... FIGURE 11-2: VOLTAGE REFERENCE BLOCK DIAGRAM V REN 8R V REF Note defined in Table 12-3. 1999 Microchip Technology Inc. 11.1 Configuring the Voltage Reference The Voltage Reference can output 16 distinct voltage levels for each range. The equations used to calculate the output of the Voltage Reference are as follows ...
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... The V value select REF Reference Module operates bit, ROE enabled will also increase REF V Output REF Value On Value On Bit 0 All Other POR Resets VR0 000- 0000 000- 0000 CM0 0000 0000 0000 0000 TRISA0 11-1 1111 11-1 1111 1999 Microchip Technology Inc. ...
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... TSR empty 0 = TSR full bit 0: TX9D: 9th bit of transmit data. Can be parity bit. 1999 Microchip Technology Inc half duplex synchronous system that can commu- nicate with peripheral devices such as A/D or D/A inte- grated circuits, Serial EEPROMs etc. The USART can be configured in the following modes: • ...
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... Overrun error (Can be cleared by clearing bit CREN overrun error bit 0: RX9D: 9th bit of received data (Can be parity bit) DS40300B-page 72 R/W-0 R-0 R-0 R-x ADEN FERR OERR RX9D bit0 Preliminary R = Readable bit W = Writable bit U = Unimplemented bit, read as ’0’ Value at POR reset x = unknown 1999 Microchip Technology Inc. ...
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... RCSTA SPEN RX9 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented read as '0'. Shaded cells are not used by the BRG. 1999 Microchip Technology Inc. EXAMPLE 12-1: CALCULATING BAUD RATE Desired Baud rate = Fosc / ( 1)) 9600 = X = Calculated Baud Rate=16000000 / (64 (25 + 1)) = ...
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... ERROR (decimal 1.203 +0.23 92 2.380 -0.83 46 9.322 -2.90 11 18.64 -2. 111 0.437 - 255 32.768 kHz SPBRG SPBRG % value % value ERROR (decimal) KBAUD ERROR (decimal) +0.16 51 0.256 -14.67 +0. -6. 0.512 - - 255 0.0020 - 255 1999 Microchip Technology Inc ...
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... KBAUD 9.6 9 19.2 18.645 -2.94 16 1.202 38.4 39.6 +3.12 7 2.403 57.6 52.8 -8.33 5 9.615 115.2 105.6 -8.33 2 19.231 250 625 1250 1999 Microchip Technology Inc. 10 MHz SPBRG SPBRG % value % value ERROR (decimal) KBAUD ERROR (decimal) +0.16 103 9.615 +0.16 64 +0.16 51 18.939 -1.36 32 +0.16 25 39.062 +1.7 15 +2.12 16 56.818 -1.36 10 -3.55 8 125 +8. ...
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... Baud CLK for all but start bit Samples bit0 Start Bit First falling edge after RX pin goes low Second rising edge Samples Samples Preliminary Bit0 bit1 Samples 1999 Microchip Technology Inc. ...
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... FIGURE 12-4: RX PIN SAMPLING SCHEME, BRGH = 0 OR BRGH = 1 RX (RB1/RX/DT pin) Baud CLK x16 CLK 1999 Microchip Technology Inc. Start Bit Baud CLK for all but start bit Second rising edge 1 2 Samples Start bit Baud CLK for all but start bit ...
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... TSR register (if the TSR is empty). In such a case, an incorrect ninth data bit maybe loaded in the TSR regis- ter. Data Bus TXREG register 8 MSb LSb (8) 0 TSR register TRMT TX9 TX9D Preliminary Pin Buffer and Control RB2/TX/CK pin SPEN 1999 Microchip Technology Inc. ...
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... CSRC TX9 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission. 1999 Microchip Technology Inc 9-bit transmission is desired, then set transmit bit TX9. 5. Enable the transmission by setting bit TXEN, which will also set bit TXIF ...
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... RCREG register in order not to lose the old FERR and RX9D information. OERR CREN 64 RSR register MSb Stop (8) Data RX9 Recovery Enable Load of Receive Buffer RX9D RCREG register RCREG register RX9D 8 RCIF Interrupt RCIE Preliminary FERR LSb 0 1 Start 8 8 FIFO Data Bus 1999 Microchip Technology Inc. ...
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... Note: This timing diagram shows an address byte followed by an data byte. The data byte is read into the RCREG (receive buffer) because ADEN was updated after an address match, and was cleared to a ‘0’, so the contents of the receive shift register (RSR) are read into the receive buffer regardless of the value of bit8. 1999 Microchip Technology Inc. Start Stop ...
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... BRGH TRMT Preliminary Value on Value on Bit 0 all other POR Resets TMR1IF 0000 -000 0000 -000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 -000 0000 -000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 1999 Microchip Technology Inc. ...
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... The receive block diagram is shown in Figure 12-8. Reception is enabled by setting bit CREN (RCSTA<4>). 1999 Microchip Technology Inc. 12.3.1.1 SETTING UP 9-BIT MODE WITH ADDRESS DETECT Steps to follow when setting up an Asynchronous or Synchronous Reception with Address Detect Enabled: 1 ...
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... TX9D is loaded. Preliminary Value on Value on all other POR Resets 0000 -000 0000 -000 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 -000 0000 -000 0000 -010 0000 -010 0000 0000 0000 0000 1999 Microchip Technology Inc. ...
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... RB1/RX/DT pin RB2/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit 1999 Microchip Technology Inc 9-bit transmission is desired, then set bit TX9. 5. Enable the transmission by setting bit TXEN 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. ...
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... TRMT Preliminary Value on: Value on all Bit 0 POR other Resets 0000 -000 0000 -000 TMR1IF 0000 -00x 0000 -00x RX9D 0000 0000 0000 0000 -000 0000 -000 -000 TMR1IE 0000 -010 0000 -010 TX9D 0000 0000 0000 0000 1999 Microchip Technology Inc. ...
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... RCIF bit (interrupt) Read RXREG Note: Timing diagram demonstrates SYNC master mode with bit SREN = ’1’ and bit BRG = ’0’. 1999 Microchip Technology Inc Q4Q1 Q4Q1 Q4Q1 bit1 bit2 bit3 ...
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... RCIE was set. 6. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. Read the 8-bit received data by reading the RCREG register any error occurred, clear the error by clearing bit CREN. Preliminary 1999 Microchip Technology Inc. ...
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... PIE1 EEIE CMIE 98h TXSTA CSRC TX9 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception. 1999 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RCIF TXIF — CCP1IF TMR2IF ...
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... PIC16F62X NOTES: DS40300B-page 90 Preliminary 1999 Microchip Technology Inc. ...
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... The upper bit is address decoded. This means that this bit should always be ’0’ to ensure that the address is in the 128 byte memory space. 1999 Microchip Technology Inc. The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write) ...
Page 92
... EECON2 is not a physical register. Reading EECON2 will read all ’0’s. The EECON2 register is used exclusively in the Data EEPROM write sequence. R/W-x R/W-0 R/S-0 R/S-x WRERR WREN WR RD bit0 Preliminary R = Readable bit W = Writable bit S = Settable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1999 Microchip Technology Inc. ...
Page 93
... WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. 1999 Microchip Technology Inc. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit ...
Page 94
... Legend unknown unchanged unimplemented read as ’0’ value depends upon condition. Shaded cells are not used by data EEPROM. Note 1: EECON2 is not a physical register DS40300B-page 94 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 — — WRERR WREN WR Preliminary Value on Value on all Bit 0 Power-on other resets Reset xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu RD ---- x000 ---- q000 ---- ---- ---- ---- 1999 Microchip Technology Inc. ...
Page 95
... SLEEP 6. Code protection 7. ID Locations 8. In-circuit serial programming 1999 Microchip Technology Inc. PIC16F62X The PIC16F62X has a Watchdog Timer which is controlled by configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in reset until the crystal oscillator is stable ...
Page 96
... The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special configuration memory space (2000h – 3FFFh), which can be accessed only during program- ming. BODEN MCLRE FOSC2 PWRTE WDTE (2) (3) (1) DD (1) (4) Preliminary F0SC1 F0SC0 Register:CONFIG Address2007h bit0 1999 Microchip Technology Inc. ...
Page 97
... Note: A series resistor may be required for AT strip cut crystals. FIGURE 14-3: EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) Clock from OSC1 ext. system PIC16F62X OSC2 Open 1999 Microchip Technology Inc. TABLE 14-1: Ranges Characterized: Mode Freq 455 kHz XT 2.0 MHz 4.0 MHz 8.0 MHz HS 16.0 MHz Higher capacitance increases the stability of the oscillator but also increases the start-up time ...
Page 98
... I/O port. The other configures the pin as an output providing the Fosc signal (internal clock divided by 4) for test or external synchronization pur- poses. Preliminary OPERATION (HS OSC CONFIGURATION) OSC1/RA7 PIC16F62X OSC2/RA6 , is SS RA7/OSC1/CLKIN RA6/OSC2/CLKOUT values. DD 1999 Microchip Technology Inc. ...
Page 99
... The OSCF bit in the PCON register is used to control dual speed mode. See Section 4.2.2.6, Figure 4-9. 1999 Microchip Technology Inc. PIC16F62X 14.4 Reset The PIC16F62X differentiates between various kinds ...
Page 100
... BODEN OST/PWRT OST 10-bit Ripple-counter OSC1/ CLKIN Pin PWRT (1) On-chip 10-bit Ripple-counter ER OSC Note 1: This is a separate oscillator from the INTRC/EC oscillator. DS40300B-page 100 Enable PWRT See Table 14-3 for time-out situations. Enable OST Preliminary 1999 Microchip Technology Inc Chip_Reset Q R ...
Page 101
... V DD Internal Reset V DD Internal Reset 1999 Microchip Technology Inc. The Power-Up Time delay will vary from chip to chip and due temperature and process variation. DD See DC parameters for details. 14.5.3 OSCILLATOR START-UP TIMER (OST) The Oscillator Start-Up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over ...
Page 102
... Bit — — OSCF — POR Preliminary may have DD Wake-up Brown-out Reset from SLEEP 1024 T 1024 T OSC OSC 72 ms — Value on all Value on POR Bit 0 (1) Reset other resets 0001 1xxx 000q quuu C BOD ---- 1-0x ---- u-uq 1999 Microchip Technology Inc. ...
Page 103
... Interrupt Wake-up from SLEEP u x Legend: = unchanged, = unknown, Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC+1. 1999 Microchip Technology Inc. Program STATUS Counter Register 000h 0001 1xxx 000h ...
Page 104
... SLEEP through interrupt • Wake up from SLEEP through (1) WDT time-out uuuu uuuu - uuuu uuuu ( (4) (4) uuuq quuu uuuu uuuu xxxx 0000 uuuu uuuu uu-- uuuu ---u uuuu (2) uuuu uqqq (2,5) -q-- ---- uuuu uuuu uu-u uuuu uuuu uuuu uuuu -uuu ---- --uu uuu- uuuu 1999 Microchip Technology Inc. ...
Page 105
... FIGURE 14-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 14-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 1999 Microchip Technology Inc. PIC16F62X T PWRT T OST T PWRT T OST ) DD T PWRT T OST ...
Page 106
... V is below a certain level such that Internal brown-out reset should be disabled when using this circuit. 3: Resistors should be adjusted for the charac- teristics of the transistor. Preliminary 1999 Microchip Technology Inc MCLR 40k PIC16F62X MCLR 40k ...
Page 107
... TXIE RCIF RCIE EEIF EEIE 1999 Microchip Technology Inc. When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits ...
Page 108
... CCP1IE TMR2IE Preliminary 0004h 0005h Inst (0005h) Inst (0004h) Value on all Value on POR Bit 0 (1) Reset other resets RBIF 0000 000x 0000 000u TMR1IF 0000 -000 0000 -000 TMR1IE 0000 -000 0000 -000 1999 Microchip Technology Inc. ...
Page 109
... W into STATUS register SWAPF W_TEMP,F ;swap W_TEMP SWAPF W_TEMP,W ;swap W_TEMP into W 1999 Microchip Technology Inc. PIC16F62X 14.8 Watchdog Timer (WDT) The watchdog timer is a free running on-chip RC oscil- lator which does not require any external components. This RC oscillator is separate from the ER oscillator of the CLKIN pin ...
Page 110
... Bit 4 Bit 3 Bit 2 Bit 1 MCLRE FOSC2 PWRTE WDTE FOSC1 T0CS T0SE PSA PS2 PS1 Preliminary 8 PS<2:0> To TMR0 (Figure 6-6) 1 PSA Value on Value on POR all other Bit 0 Reset Resets FOSC0 uuuu uuuu uuuu uuuu PS0 1111 1111 1111 1111 1999 Microchip Technology Inc. ...
Page 111
... GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line. 4: CLKOUT is not available in these osc modes, but shown here for timing reference. 1999 Microchip Technology Inc. The first event will cause a device reset. The two latter events are considered a continuation of program exe- cution ...
Page 112
... It should be noted, that once the LVP bit is programmed to 0, only the high voltage programming mode is avail- able and only high voltage programming mode can be used to program the device. Preliminary To Normal Connections PIC16F62X RA5/MCLR/THV RB6 RB7 IHH IHH must be IHH 1999 Microchip Technology Inc. ...
Page 113
... Assigned to < > Register bit field In the set of i talics User defined term (font is courier) 1999 Microchip Technology Inc. PIC16F62X The instruction set is highly orthogonal and is grouped into three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations ...
Page 114
... Preliminary 1999 Microchip Technology Inc. Status Notes Affected LSb C,DC,Z 1,2 ffff Z 1,2 ffff Z 2 ffff Z 0011 Z 1,2 ffff Z 1,2 ffff 1,2,3 ffff Z 1,2 ffff 1,2,3 ffff Z ...
Page 115
... Words: 1 Cycles: 1 Example ADDWF FSR, 0 Before Instruction W = 0x17 FSR = 0xC2 After Instruction W = 0xD9 FSR = 0xC2 1999 Microchip Technology Inc. ANDLW k Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: . Words: Cycles: Example ANDWF f,d Syntax: Operands: Operation: ...
Page 116
... Words: 1 Cycles: 1(2) Example Before Instruction After Instruction ffff 7 Preliminary f 127 10bb bfff ffff . HERE BTFSC FLAG,1 FALSE GOTO PROCESS_CODE TRUE • • • address HERE if FLAG<1> address TRUE if FLAG<1>= address FALSE 1999 Microchip Technology Inc. ...
Page 117
... PC are loaded from PCLATH. CALL is a two-cycle instruction. Words: 1 Cycles: 2 Example HERE CALL THERE Before Instruction PC = Address HERE After Instruction PC = Address THERE TOS = Address HERE+1 1999 Microchip Technology Inc. CLRF Syntax: Operands: Operation: Status Affected: Encoding: bfff ffff Description: Words: Cycles: Example CLRW Syntax: ...
Page 118
... A NOP is executed instead making it a two-cycle instruction. 1 1(2) HERE DECFSZ CNT, 1 GOTO LOOP CONTINUE • • • Before Instruction address PC = HERE After Instruction CNT = CNT - 1 if CNT = address CONTINUE if CNT address HERE+1 1999 Microchip Technology Inc. ...
Page 119
... Words: 1 Cycles: 1 Example INCF CNT, 1 Before Instruction CNT = Z = After Instruction CNT = Z = 1999 Microchip Technology Inc. INCFSZ Syntax: Operands: Operation: Status Affected: Encoding: kkkk Description: Words: Cycles: Example IORLW Syntax: Operands: Operation: Status Affected: Encoding: ffff ...
Page 120
... MOVF FSR, 0 After Instruction W = value in FSR register Move label ] MOVWF 127 (W) (f) None 00 0000 1fff ffff Move data from W register to register . ' MOVWF OPTION Before Instruction OPTION = 0xFF W = 0x4F After Instruction OPTION = 0x4F W = 0x4F 1999 Microchip Technology Inc. ...
Page 121
... PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it. Words: 1 Cycles: 1 Example To maintain upward compatibility with future PICmicro not use this instruction. 1999 Microchip Technology Inc. RETFIE Syntax: Operands: Operation: Status Affected: 0000 Encoding: Description: Words: Cycles: Example ...
Page 122
... The power-down status bit cleared. Time-out status bit set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. See Section 14.9 for more details SLEEP 1999 Microchip Technology Inc. ...
Page 123
... result is zero Example 3: Before Instruction After Instruction W = 0xFF result is nega- tive 1999 Microchip Technology Inc. SUBWF Subtract W from f Syntax: [ label ] Operands [0,1] Operation: (f) - (W) Status C, DC, Z Affected: kkkk Encoding: 00 Description: Subtract (2’s complement method) W register from register 'f the result is stored in the W register ...
Page 124
... Exclusive OR the contents of the W register with register 'f the result is stored in the W register the result is stored back in register 'f XORWF REG 1 Before Instruction REG = 0xAF W = 0xB5 After Instruction REG = 0x1A W = 0xB5 1999 Microchip Technology Inc. ...
Page 125
... A full featured editor • A project manager • Customizable tool bar and key mapping • A status bar • On-line help 1999 Microchip Technology Inc. PIC16F62X MPLAB allows you to: • Edit your source files (either assembly or ‘C’) • One touch assemble (or compile) and download ...
Page 126
... PICmicro MCU. 16.7 PICMASTER/PICMASTER CE The PICMASTER system from Microchip Technology is a full-featured, professional quality emulator system. This flexible in-circuit emulator provides a high-quality, universal platform for emulating Microchip 8-bit PICmicro microcontrollers (MCUs). PICMASTER sys- tems are sold worldwide, with a CE compliant model available for European Union (EU) countries ...
Page 127
... SIMICE is an entry-level hardware development sys- tem designed to operate in a PC-based environment with Microchip’s simulator MPLAB-SIM. Both SIMICE and MPLAB-SIM run under Microchip Technology’s MPLAB Integrated Development Environment (IDE) software. Specifically, SIMICE provides hardware sim- ulation for Microchip’s PIC12C5XX, PIC12CE5XX, and PIC16C5X families of PICmicro 8-bit microcontrollers ...
Page 128
... K L evaluation and programming tools support EE OQ Microchips HCS Secure Data Products. The HCS eval- uation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a pro- gramming interface to program test transmitters. DS40300B-page 128 PIC17C756, Preliminary 1999 Microchip Technology Inc. ...
Page 129
... PIC16C6X á á á á PIC16C5X á á á á PIC14000 á á á á PIC12CXXX Tools Software Emulators 1999 Microchip Technology Inc. á á á á á á á á á á á á á á á á á á ...
Page 130
... PIC16F62X NOTES: DS40300B-page 130 Preliminary 1999 Microchip Technology Inc. ...
Page 131
... Exposure to maximum rating conditions for extended periods may affect device reliability. Note: Voltage spikes below V SS Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR pin rather than pulling this pin directly to V 1999 Microchip Technology Inc. ..........................................................................................-0.3 to +14V SS ....................................................................................-0. ...
Page 132
... Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 17-2: PIC16F62X VOLTAGE-FREQUENCY GRAPH, -40 C 6.0 5.5 5.0 4 (Volts) 4.0 3.5 3.0 2.5 2.0 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. DS40300B-page 132 Frequency (MHz Frequency (MHz) Preliminary + + 1999 Microchip Technology Inc. ...
Page 133
... Note 1: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 17-4: PIC16LF62X VOLTAGE-FREQUENCY GRAPH, -40 C 6.0 5.5 5.0 4 (Volts) 4.0 3.5 3.0 2.5 2.0 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 1999 Microchip Technology Inc Frequency (MHz Frequency (MHz) Preliminary PIC16F62X + +70 C ...
Page 134
... See section on power-on reset for details BODEN configuration bit is cleared (Extended 4 3.0 OSC 20.0 MHz 5.5 OSC 20.0 MHz 4.5 OSC 10.0 MHz 3.0 OSC 5.5 Extended DD V =4.0V DD (125 C) BOD enabled 5. 4. 4.0V DD All temperatures All temperatures All temperatures All temperatures , . SS 1999 Microchip Technology Inc. ...
Page 135
... For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the for- mula /2Rext (mA) with Rext 1999 Microchip Technology Inc. PIC16LF62X-04 (Commercial, Industrial, Extended) TA +85°C for industrial and 0°C TA +70°C for commercial and – ...
Page 136
... =7.0 mA, V =4.5V, +125 =1.6 mA, V =4.5V, - =1.2 mA, V =4.5V, +125 =-3.0 mA, V =4.5V, - =-2.5 mA, V =4.5V, +125 =-1.3 mA, V =4.5V, - =-1.0 mA, V =4.5V, +125 RA4 pin PIC16F62X, PIC16LF62X clock used to drive OSC1. 1999 Microchip Technology Inc. ...
Page 137
... Absolute Accuracy D312 Unit Resistor Value (R)* 310 (1)* Settling Time * These parameters are characterized but not tested. Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111. 1999 Microchip Technology Inc. V 5.5V, -40°C < T < +125°C, unless otherwise stated Sym Min ...
Page 138
... Standard Operating Conditions (unless otherwise stated) Min Typ† Max 1M 10M — — 5.5 MIN — 1000 10000 — * Vmin — 5.5 4.5 — 5.5 — Preliminary Units Conditions E Minimum operating MIN voltage ms E Minimum operating MIN voltage V ms 1999 Microchip Technology Inc. ...
Page 139
... Oscillator Period (Note 1) 2 Tcy Instruction Cycle Time (Note 1) 1.0 3 TosL, External CLKIN (OSC1) High TosH External CLKIN Low 4 INTRC Internal Calibrated External Biased ER Frequency 10kHz 1999 Microchip Technology Inc Min Typ† Max DC — — ...
Page 140
... new value Typ† Max Units 75 200 ns — 400 ns 75 200 ns — 400 ns 35 100 ns — 200 ns 35 100 ns — 200 ns — — — ns — — ns — — 150 * ns — 300 ns — — ns 1999 Microchip Technology Inc. ...
Page 141
... Prescaler) 32 Tost Oscillation Start-up Timer Period 33* Tpwrt Power up Timer Period 34 T I/O Hi-impedance from MCLR Low IOZ or Watchdog Timer Reset 35 T Brown-out Detect pulse width BOD 1999 Microchip Technology Inc. PIC16F62X Unit Min Typ† Max s 2000 — — ...
Page 142
... PIC16F62X FIGURE 17-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI RB6/T1OSO/T1CKI TMR0 or TMR1 DS40300B-page 142 Preliminary 1999 Microchip Technology Inc. 48 ...
Page 143
... These parameters are characterized but not tested. †Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 17-11: CAPTURE/COMPARE/PWM TIMINGS RB3/CCP1 (Capture Mode) RB3/CCP1 (Compare or PWM Mode) 1999 Microchip Technology Inc. Min No Prescaler 0. With Prescaler 10 No Prescaler 0 ...
Page 144
... CY With Prescaler 10* — — 40* — — Preliminary Conditions — ns — ns — ns — ns — ns — ns — prescale value (1 Units Conditions prescale value ( ..., 256) 1999 Microchip Technology Inc. ...
Page 145
... DEVICE CHARACTERIZATION INFORMATION Not Available at this time. 1999 Microchip Technology Inc. PIC16F62X Preliminary DS40300B-page 145 ...
Page 146
... PIC16F62X NOTES: DS40300B-page 146 Preliminary 1999 Microchip Technology Inc. ...
Page 147
... Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 1999 Microchip Technology Inc. PIC16F62X Example PIC16F627 -04I / P456 9923 CBA Example PIC16F627 -04I / S0218 9918 CDK Example PIC16F627 -04I / 218 9951 CBP Preliminary DS40300B-page 147 ...
Page 148
... A1 0.075 0.095 0.115 A2 0.000 0.020 0.020 L 0.125 0.130 0.135 ‡ D 0.890 0.895 0.900 ‡ E 0.245 0.255 0.265 E1 0.230 0.250 0.270 eB 0.310 0.349 0.387 Preliminary MILLIMETERS MIN NOM MAX 7.62 18 2.54 0.33 0.46 0.58 1.40 1.52 1.65 0.00 0.13 0.25 0.13 0.25 0.38 2.79 3.94 3.94 1.91 2.41 2.92 0.00 0.51 0.51 3.18 3.30 3.43 22.61 22.73 22.86 6.22 6.48 6.73 5.84 6.35 6.86 7.87 8.85 9. 1999 Microchip Technology Inc. ...
Page 149
... Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” 1999 Microchip Technology Inc ...
Page 150
... Preliminary A1 NOM MAX 0.65 20 1.86 1.99 0.91 1.17 0.13 0.21 7.20 7.33 5.29 5.38 7.78 7.90 0.13 0.25 0.13 0.25 0.51 0. 0.13 0.25 0.18 0.22 0.32 0. 1999 Microchip Technology Inc. ...
Page 151
... Clocking Scheme/Instruction Cycle .................................... 12 CLRF Instruction ............................................................... 117 CLRW Instruction .............................................................. 117 CLRWDT Instruction ......................................................... 118 CMCON Register ................................................................ 57 Code Protection ................................................................ 112 COMF Instruction .............................................................. 118 Comparator Configuration................................................... 58 1999 Microchip Technology Inc. PIC16F62X Comparator Interrupts......................................................... 61 Comparator Module ............................................................ 57 Comparator Operation ........................................................ 59 Comparator Reference ....................................................... 59 Compare (CCP Module) ..................................................... 65 Block Diagram ............................................................ 65 CCP Pin Configuration ............................................... 65 CCPR1H:CCPR1L Registers ...
Page 152
... Special ................................................................................ 99 Special Features of the CPU .............................................. 95 Special Function Registers ................................................. 15 Stack................................................................................... 25 Status Register ................................................................... 19 SUBLW Instruction ........................................................... 123 SUBWF Instruction ........................................................... 123 SWAPF Instruction ........................................................... 124 T T1CKPS0 bit ....................................................................... 50 T1CKPS1 bit ....................................................................... 50 T1CON Register ................................................................. 50 T1OSCEN bit ...................................................................... 50 T1SYNC bit......................................................................... 50 T2CKPS0 bit ....................................................................... 55 T2CKPS1 bit ....................................................................... 55 T2CON Register ................................................................. 55 Preliminary 1999 Microchip Technology Inc. ...
Page 153
... TXSTA Register .................................................................. 71 U Universal Synchronous Asynchronous Receiver Transmitter (USART) .......................................................... 71 Asynchronous Receiver Setting Up Reception .......................................... 83 Timing Diagram .................................................. 81 Asynchronous Receiver Mode Block Diagram .................................................... 83 Section ................................................................ 83 1999 Microchip Technology Inc. PIC16F62X USART Asynchronous Mode................................................... 78 Asynchronous Receiver.............................................. 80 Asynchronous Reception............................................ 82 Asynchronous Transmission ...................................... 79 Asynchronous Transmitter.......................................... 78 Baud Rate Generator (BRG) ...................................... 73 Sampling..................................................................... 76 Synchronous Master Mode ...
Page 154
... PIC16F62X DS40300B-page 154 Preliminary 1999 Microchip Technology Inc. ...
Page 155
... Trademarks: The Microchip name, logo, PIC, PICmicro, PICSTART, PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Flex ROM, MPLAB and fuzzy- LAB are trademarks and SQTP is a service mark of Micro- chip in the U ...
Page 156
... Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS40300B-page 156 Total Pages Sent FAX: (______) _________ - _________ N Literature Number: DS40300B Preliminary 1999 Microchip Technology Inc. ...
Page 157
... Reel) DD PIC16LF62X:V range 2.0V to 5.5V DD PIC16LF62XT:V range 2.0V to 5.5V (Tape and Reel) DD Preliminary PIC16F62X Examples: g) PIC16F627 - 04/P 301 = Commercial temp., PDIP pack- age, 4 MHz, normal V limits, DD QTP pattern #301. h) PIC16LF627- 04I/SO = Industrial temp., SOIC pack- age, 200kHz, extended V DD limits. DS40300B-page 157 ...
Page 158
... PIC16F62X NOTES: DS40300B-page 158 1999 Microchip Technology Inc. ...
Page 159
... NOTES: 1999 Microchip Technology Inc. PIC16F62X Preliminary DS40300B-page 159 ...
Page 160
... Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip ...