ISL9N306AP3 Fairchild Semiconductor, ISL9N306AP3 Datasheet - Page 8

• Manufacturer Part Number: ISL9N306AP3
• Description: N-channel Logic Level PWM Optimized UltraFET Trench Power MOSFETs
• Manufacturer: Fairchild Semiconductor

©2002 Fairchild Semiconductor Corporation
PSPICE Electrical Model
.SUBCKT ISL9N306A 2 1
CA 12 8 2.0e-9
CB 15 14 2.3e-9
CIN 6 8 3e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 35.8
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN 2 5 1.0e-9
LGATE 1 9 4.58e-9
LSOURCE 3 7 1.47e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1e-3
RGATE 9 20 2.69
RLDRAIN 2 5 10
RLGATE 1 9 45.8
RLSOURCE 3 7 14.7
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 3.5e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*275),5))}
.MODEL DBODYMOD D (IS = 3.6e-11 N=1.07 5RS = 3.5e- 3TRS1 = 1e- 3TRS2 = 1e-6 XTI=1. 0CJO = 1.45e- 9TT = 8e-11 M =
0.51)
.MODEL DBREAKMOD D (RS = 1.7e- 1TRS1 = 1e- 3TRS2 = -8.9e-6)
.MODEL DPLCAPMOD D (CJO = 11.5e-1 0IS = 1e-3 0N = 10 M = 0.46)
.MODEL MMEDMOD NMOS (VTO = 1.7 KP = 9 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.69)
.MODEL MSTROMOD NMOS (VTO = 2.1 KP = 100 IS = 1e-30 N= 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.36 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 26.9 RS = .1)
.MODEL RBREAKMOD RES (TC1 = 1e- 3TC2 = -7e-7)
.MODEL RDRAINMOD RES (TC1 = 1.2e- 2TC2 = 3.0e-5)
.MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2.6e-3 TC2 = -7.5e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.8e- 3TC2 = 1e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.0 VOFF= -0.8)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.8 VOFF= -4.0)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.3 VOFF= 0.2)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.2 VOFF= -0.3)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
GATE
1
3 ;rev May 2001
RLGATE
LGATE
9
RGATE
CA
12
20
EVTEMP
+
S1B
S1A
ESG
18
22
EGS
13
8
+
-
-
13
6
8
10
+
+
-
-
14
13
6
8
RSLC2
6
S2A
S2B
DPLCAP
EVTHRES
+
EDS
19
8
15
CB
CIN
-
+
-
5
8
51
5
5
MSTRO
14
+
-
51
21
RDRAIN
RSLC1
50
ESLC
16
8
MMED
8
EBREAK
IT
DBREAK
RSOURCE
MWEAK
17
RVTHRES
RBREAK
11
+
-
17
18
7
+
18
-
22
RVTEMP
19
RLSOURCE
RLDRAIN
DBODY
LSOURCE
VBAT
LDRAIN
SOURCE
DRAIN
Rev. B, February 2002
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3