SDA9380 Micronas Intermetall GmbH, SDA9380 Datasheet - Page 2

• Manufacturer Part Number: SDA9380
• Description: Enhanced Deflection Controller And RGB Video Processor (EDDC)
• Manufacturer: Micronas Intermetall GmbH

SDA 9380 - B21
Document Change Note
Micronas
DS
2
3
1
31.03.98
17.07.98
23.07.98
23.07.98
27.07.98
07.08.98
09.09.98
14.09.98
16.09.98
16.09.98
16.09.98
16.09.98
16.09.98
18.09.98
18.09.98
18.09.98
18.09.98
20.10.98 1, 3, 10, 39 18.75 kHz line frequency added
27.10.98
12.11.98
19.11.98
24.11.98
02.12.98
04.12.98
04.12.98
04.12.98
18.01.99
21.01.99
21.01.99
22.01.99
05.02.99
26.02.99
15.03.99
15.03.99
15.03.99
16.03.99
Date
14, 17, 20 Description of PMW byte changed
10, 21, 39 I²C bit HSWID deleted
10, 21, 39 I²C bit HSWMI added
14, 31, 32 End of V-blanking also programmable by VBE if JMP=0
2, 14, 46
1, 7, 11
4, 5, 6
25, 26
10, 39
15, 43
15, 44
14,15
Page
5, 6
7, 8
46
27
43
24
20
34
21
31
21
40
40
39
15
19
11
37
43
3
4
Version 02
Document state 03 corresponds to silicon version A11
block diagram changed
bandwidth of YUV increased (new value 30 MHz)
Vertical component of SCP changed (not equals internal signal VBL!)
Pin configuration changed
SCP output level changed (supply voltage for SCP is V
Sequence of I²C control items changed, new items added
Bit SLBLKS added to RGB control byte 1
Detailed description of the I²C item PWM control byte
Detailed description of the items Average beam current limit character-
istics, Peak drive limit, Soft clipping
Explanation of the items Peak dark detection top border, bottom border,
left border, right border
I²C bit KILLZIP deleted, KILLZIP function remains implemented
Positive and negative polarity of HSYNC allowed (int. normalization)
Specification of end of V-blanking component of SCP changed
3 MSBs of PLL control byte 1 must be 0 instead of don’t care
Pin configuration changed
HSAFE input voltage at 31.25 kHz and 38 kHz specified
VREFP, VREFH, VREFL are internal reference voltages
Input BSOIN, delay t
Default value of saturation control changed form 0 to -12
I²C bus bits NR, NL2...NL0 of Vertical sync byte control deleted
Text changed because the vertical noise reduction has been removed
Remark for switching to external clock mode added
Pin description changed
Description of Black Switch Off (BSO) changed
VSS, SUBST total voltage differentials added
Higher resolution of D/A output (6 bit -> 8 bit), INL changed (1 -> 2 LSB)
Contrast setting with resolution of 8 bit instead of 6 bit
Brightness setting with resolution of 8 bit instead of 6 bit
NTSC/US matrix changed
Changes compared to previous issue
D2
changed from 30 lines to 42 lines
i
Preliminary Data sheet
DD(MC)
2001-05-03