SDA9380 Micronas Intermetall GmbH, SDA9380 Datasheet - Page 18

• Manufacturer Part Number: SDA9380
• Description: Enhanced Deflection Controller And RGB Video Processor (EDDC)
• Manufacturer: Micronas Intermetall GmbH

SDA 9380 - B21
Preliminary Data Sheet
System description
5.1.2 RGB processing
To provide an accurate biasing of the picture tube the offsets and gains of the RGB output stages
are continuously adjusted by a cut off and white level control loop. Leakage, cut off and white current
are measured each frame during vertical flyback at the DCI input. The position of the measurement
lines is adjustable by IIC bus (see page 31). The reference currents for the cut off and white levels
are adjusted by IIC bus with a 6 bit parameter for each output and a common 3 bit gain parameter.
Because the video amplifiers are part of the control loops, the overall gain and offset is no more
adjustable in this stage. For proper dimensioning of the video amplifiers there is an IIC status bit
(CLOW), which is 0 when all offset and gain actuators of the RGB outputs are within 50% of its full
range. The control loops can be switched to halt mode to switch off the measurement lines in verti-
cal shrink mode. When the TV screen is switched on brightness and contrast ramp up in a soft start
mode as soon as the cut off control loop is locked.
There are three circuits implemented for beam current limiting:
-First there is a circuit for accurate average beam current limiting. The beam current is measured at
the Ibeam input and limited by reducing first contrast and, after half contrast is reached, brightness
too. All parameters (limit value, gain, up time constant and down time constant) are adjustable by IIC
bus.
-Second a peak drive limiter circuit is implemented for the higher frequency content of the video sig-
nal. It reduces contrast when a limit value is exceeded by the R, G or B video signals. Also all
parameters (limit value, up time constant and down time constant) are adjustable by IIC bus.
-Third there is a soft clipper for the very high frequency content of the video signal. It limits the R, G
or B video signals according to the diagram at 11.7. Limit value and slope are adjustable by IIC bus.
The TV screen can be switched to blue by IIC bus when no video signal is available.
When the blue stretch function is activated by IIC bus, the gain of the red and green output is
reduced by 17% for amplitudes more than 80% of the nominal amplitude. This shifts white towards
light blue.
A black stretch function (switchable by IIC bus) stretches video signals with a black level which is
higher than the clamping level towards black. Therefore the peak dark value of the video signal is
stored. The height of the peak dark value determines the amount of stretch (diagram at 11.6). The
screen area in which the peak dark detector is enabled is programmable by IIC bus. So it is possible
to screen black borders of the picture (e.g. letter box format) which otherwise prevent the desired
function of black stretch.
An overall luminance output is provided for supplying a circuit for scan velocity modulation. The
delay of the RGB outputs to the luminance output is adjustable by IIC bus. So a proper alignment of
the video signals and the current in the SVM coil is possible.
Micronas
5-10
2001-05-03