SDA9380 Micronas Intermetall GmbH, SDA9380 Datasheet - Page 19

• Manufacturer Part Number: SDA9380
• Description: Enhanced Deflection Controller And RGB Video Processor (EDDC)
• Manufacturer: Micronas Intermetall GmbH

SDA 9380 - B21
5.2
The HSYNC is reference for a numeric PLL. This PLL generates a clock which is phase locked to
the incoming horizontal sync pulse and exactly 864 times faster than the horizontal frequency. The
polarity of the external horizontal sync pulses may be positive (see figure below) or negative. In
case of negative polarity the incoming HSYNC signal is automatically inverted for an easier applica-
tion in VGA or SVGA mode.
Incoming signal HSYNC (internal clock)
Pulse width t
Pulse width t
(The specified pulse width depends on the I²C-bus bits INCR4...INCR0 rsp. PLL clock frequency.
The above values are valid for INCR = 6. For higher INCR values the allowed pulse width is
decreasing proportional to the increasing PLL clock frequency.)
The described input signal is first applied to an A/D converter. Conversion takes place with 7 bits
and a nominal frequency of 27 MHz. The digital PLL uses a low pass filter to obtaine defined slopes
for further measurements (PAL/NTSC applications). In addition the actual high and low level of the
signal as well as a threshold value is evaluated and used to calculate the phase error between inter-
nal clock and external horizontal sync pulse. By means of digital PI filtering an increment is gained
from this. The PI filter can be set by the I
optimal in relation to either the TV or VCR mode. Moreover it is possible to adapt the nominal fre-
quency by means of 5 I
bus bit GENMOD offers the possibility to use the PLL as a frequency generator which frequency is
controlled by the INCR bits.
Micronas
Circuit description
w
w
for I
for I
2
2
C-bus Bit ’HSWMI’=0:
C-bus Bit ’HSWMI’=1:
1.5
3.0
0.8
1.7
2
µ
µ
µ
µ
C-bus bits (INCR4..INCR0) to different horizontal frequencies. An additional
s ... 4.5
s ... 9.0
s ... 4.5
s ... 9.0
µ
µ
µ
µ
s (High or Low level)
s (High or Low level)
s (High or Low level)
s (High or Low level)
t
W
2
C-bus VCR bit so that the lock-in behaviour of the PLL is
5-11
FH1_2 = High
FH1_2 = Low
FH1_2 = High
FH1_2 = Low
V
Preliminary Data Sheet
HSpp
System description
V
V
HSmax
HSmin
2001-05-03