74ABT16541CMTD Fairchild Semiconductor, 74ABT16541CMTD Datasheet
74ABT16541CMTD
Specifications of 74ABT16541CMTD
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74ABT16541CMTD Summary of contents
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... MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 74ABT16541CMTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...
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Truth Tables Inputs – Inputs – ...
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Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 2) Input Current (Note Voltage Applied to Any Output ...
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DC Electrical Characteristics Symbol Parameter V Maximum LOW Level Dynamic Input Voltage ILD Note 3: Guaranteed but not tested. Note 4: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. One output at LOW. ...
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Skew Symbol Parameter t Pin to Pin Skew OSHL (Note 13) HL Transitions t Pin to Pin Skew OSLH (Note 13) LH Transitions t Duty Cycle PS (Note 14) LH–HL Skew t Pin to Pin Skew OST (Note 13) LH/HL ...
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AC Loading * Includes jig and probe capacitance FIGURE 1. Standard AC Test Load Amplitude 3.0V FIGURE 3. Test Input Signal Requirements AC Waveforms FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions FIGURE 5. Propagation Delay, Pulse Width ...
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Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 7 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...