TS68040 ATMEL Corporation, TS68040 Datasheet - Page 30

• Manufacturer Part Number: TS68040
• Description: 32-bit Mpu, 25-33 MHZ
• Manufacturer: ATMEL Corporation

TS 68040
Figure 21 : Cache organization overview.
The caches are accessed by physical addresses from the on-chip MMUs. The translation of the upper bits of the logical
address occurs concurrently with the accesses into the set array in the cache by the lower address bits. The output of the
ATC is compared with the tag field in the cache to determine if one of the lines in the selected set matches the translated
physical address. If the tag matches and the entry is valid, then the cache has a hit.
If the cache hits and the access is a read, the appropriate long word from the cache line is multiplexed onto the appropriate
internal bus. If the cache hits and the access is a write, the data, regardless of size, is written to the appropriate portion of
the corresponding longword entry in the cache.
When a data cache miss occurs and a previously valid cache line is needed to cache the new line, any dirty data in the
old line will be internally buffered and copied back to memory after the new cache line has been loaded.
Pushing of dirty data can be forced by the CPUSH instruction.
Cachability of data in each memory page is controlled by two bits in the page descriptor for each page. Cachable pages
may be either writethrough or copyback, with no write-allocate for misses to writethrough pages. Non-cachable pages may
also be specified as noncachable I O, forcing accesses to these pages to occur in order of instruction execution.
6.4.2 - Cache coherency
The TS 68040 has the ability to snoop the external bus during accesses by other bus masters to maintain coherency between
the TS 68040’s caches and external memory systems. External write cycles are snooped by both the instruction cache and
data cache ; whereas, external read cycles are snooped only by the data cache. In addition, external cycles can be flagged
on the bus as snoopable or nonsnoopable. When an external cycle is marked as snoopable, the bus snooper checks the
caches for a coherency conflict based on the state of the corresponding cache line and the type of external cycle.
Although the internal execution units and the bus snooper circuit all have access to the on-chip caches, the snooper has
priority over the execution units to allow the snooper to resolve coherency discrepancies immediately.
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