TS68040 ATMEL Corporation, TS68040 Datasheet - Page 29

• Manufacturer Part Number: TS68040
• Description: 32-bit Mpu, 25-33 MHZ
• Manufacturer: ATMEL Corporation

Table 21 - Floating-point instructions
The TS 68040 floating-point instructions, a commonly used subset of the TS 68882 instruction set, are implemented in
hardware. The remaining unimplemented instructions are less frequently used and are efficiently emulated in software, main-
taining compatibility with the TS 68881 / TS 68882 floating-point coprocessors.
The TS 68040 instruction set includes MOVE16, a new user instruction that allows high-speed transfers of 16-byte blocks
between external devices such as memory to memory or coprocessor to memory.
6.4 - Instruction and data caches
Studies have shown that typical programs spend much of their execution time in a few main routines or tight loops. Earlier
members of the TS 68000 Family took advantage of this locality of reference phenomenon to varying degrees. The TS 68040
takes further advantage of cache technology with its two, independent, on-chip, physical address space caches, one for
instructions and one for data. The caches reduce the processor’s external bus activity and increase CPU throughput by
lowering the effective memory access time. For a typical system design, the large caches of the TS 68040 yield a very high
hit rate, providing a substantial increase in system performance. Additionally, the caches are automatically burstfilled from
the external bus whenever a cache miss occurs.
The autonomous nature of the caches allows instruction-stream fetches, data-stream fetches, and a third external access to
occur simultaneously with instruction execution. For example, if the TS 68040 requires both an instruction-stream access and
an external peripheral access and if the instruction is resident in the on-chip cache, the peripheral access proceeds unimpeded
rather than being queued behind the instruction fetch. If a data operand is also required and if it is resident in the data
cache, it can also be accessed without hindering either the instruction access from its cache or the peripheral access external
to the chip. The parallelism inherent in the TS 68040 also allows multiple instructions that do not require any external accesses
to execute concurrently while the processor is performing an external access for a previous instruction.
6.4.1 - Cache organization
The instruction and data caches are four-way set-associative with 64 sets of four, 16-byte lines for a total cache storage of
4K bytes each. As shown in Figure 21, each 16-byte line contains an address tag and state information. State information
for each entry consists of a valid flag for the entire line in both instruction and data caches and write status for each long
word in the data cache. The write status in the data cache signifies whether or not the long-word data is dirty (meaning that
the data in the cache has been modified but has not been written back to external memory) for data in copyback pages.
*FABS
*FADD
*FBcc
*FCMP
*FDBcc
*FDIV
*FMOVE
*FMOVEM
*FMUL
Mnemonic
Floating-point absolute value
Floating-point add
Branch on floating-point condition
Floating-point compare
Floating-point decrement and branch
Floating-point divide
Move floating-point register
Move multiple floating-point registers
Floating-point multiply
Description
*FNEG
*FRESTORE
*FSAVE
*FScc
**FSQRT
*FSUB
*FTRAPcc
*FTST
* TS 68040 additions or alterations to the TS 68030
*
Mnemonic
and TS 68881 / TS 68882 instruction sets.
Floating-point negate
Restore floating-point internal state
Save floating-point internal state
Set according to floating-point condition
Floating-point Square Root
Floating-point substract
Trap on floating-point condition
Floating-point test
Description
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