TS68040 ATMEL Corporation, TS68040 Datasheet - Page 25

• Manufacturer Part Number: TS68040
• Description: 32-bit Mpu, 25-33 MHZ
• Manufacturer: ATMEL Corporation

TS 68040
6 - FUNCTIONAL DESCRIPTION
6.1 - Programming model
The TS 68040 integrates the functions of the integer unit, MMU, and FPU. As shown in Figure 20, the registers depicted in
the programming model provide access and control for the three units. The registers are partitioned into two levels of privilege :
user and supervisor. User programs, executing in the user mode, can only use the resources of the user model. System
software, executing in the supervisor mode, has unrestricted access to all processor resources.
The integer portion of the user programming model, consisting of 16, general-purpose, 32-bit registers and two control
registers, is the same as the user programming model of the TS 68030. The TS 68040 user programming model also incor-
porates the TS 68882 programming model consisting of eight, floating-point, 80-bit data registers, a floating-point control
register, a floating-point status register, and a floating-point instruction address register.
The supervisor programming model is used exclusively by TS 68040 system programmers to implement operating system
functions, I/O control, and memory management subsystems. This supervisor / user distinction in the TS 68000 architecture
was carefully planned so that all application software can be written to execute in the nonprivileged user mode and migrate
to the TS 68040 from any TS 68000 platform without modification. Since system software is usually modified by system
designers when porting to a new design, the control features are properly placed in the supervisor programming model. For
example, the transparent translation registers of the TS 68040 can only be read or written by the supervisor software ; the
programming resources of user application programs are unaffected by the existence of the transparent translation registers
Registers D0-D7 are data registers containing operands for bit and bit field (1 to 32 bits), byte (8 bit), word (16 bit), long-word
(32 bit), and quad-word (64 bit) operations. Registers A0-A6 and the stack pointer registers (user, interrupt, and master) are
address registers that may be used as software stack pointers or base address registers. Register A7 is the user stack
pointer in user mode, and is either the interrupt or master stack pointer (A7’ or A7’’) in supervisor mode. In supervisor mode,
the active stack pointer (interrupt or master) is selected based on a bit in the status register (SR). The address registers
may be used for word and long-word operations, and all of the 16 general-purpose registers (D0-D7, A0-A7 in Figure 20)
may be used as index registers.
The eight, 80-bit, floating-point data registers (FP0-FP7) are analogous to the integer data registers (D0-D7) of all TS 68000
Family processors. Floating-point data registers always containt extended-precision numbers. All external operands, regardless
of the data format, are converted to extended-precision values before being used in any floating-point calculation or stored
in a floating-point data register.
The program counter (PC) usually contains the address of the instruction being executed by the TS 68040. During instruction
execution and exception processing, the processor automatically increments the contents of the PC or places a new value
in the PC, as appropriate. The status register (SR in the supervisor programming model) contains the condition codes that
reflect the results of a previous operation and can be used for conditional instruction execution in a program. The lower byte
of the SR is accessible in user mode as the condition code register (CCR). Access to the upper byte of the SR is restricted
to the supervisor mode.
As part of exception processing, the vector number of the exception provides an index into the exception vector table. The
base address of the exception vector table is stored in the vector base register (VBR). The displacement of an exception
vector is added to the value in the VBR when the TS 68040 accesses the vector table during exception processing.
Alternate function code registers, SFC and DFC (source and destination), contain 3-bit function codes. Function codes can
be considered extensions of the 32-bit linear address. Function codes are automatically generated by the processor to select
address spaces for data and program accesses at the user and supervisor modes. The alternate function code registers are
used by certain instructions to explicitly specify the function codes for various operations. The cache control register (CACR)
controls enabling of the on-chip instruction and data caches of the TS 68040.
The supervisor root pointer (SRP) and user root pointer (URP) registers point to the root of the address translation table
tree to be used for supervisor mode and user mode accesses. The URP is used if FC2 of the logical address is zero, and
the SRP is used if FC2 is one.
The translation control register (TC) enables logical-to-physical address translation and selects either 4K or 8K page sizes.
As shown in Figure 20, there are four transparent translation registers - ITT0 and ITT1 for instruction accesses and DTT0
and DTT1 for data accesses. These registers allow portions of the logical address space to be transparently mapped and
accessed without the use of resident descriptors in an ATC. The MMU status register (MMUSR) contains status information
from the execution of a PTEST instruction. The PTEST instruction searches the translation tables for the logical address as
specified by this instruction’s effective address field and the DFC.
The 32-bit floating-point control register (FPCR) contains an exception enable byte that enables disables traps for each class
of floating-point exceptions and a mode byte that sets the user-selectable modes. The FPCR can be read or written to by
the user and is cleared by a hardware reset or a restore operation of the null state. When cleared, the FPCR provides the
IEEE 754 standard defaults. The floating-point status register (FPSR) contains a condition code byte, quotient bits, an ex-
ception status byte, and an accrued exception byte. All bits in the FPSR can be read or written by the user. Execution of
most floating-point instructions modifies this register.
For the subset of the FPU instructions that generate exception traps, the 32-bit floating-point instruction address register
(FPIAR) is loaded with the logical address of an instruction before the instruction is executed. This address can then be
used by a floating-point exception handler to locate a floating-point instruction that has caused an exception. The move
floating-point data register (FMOVE) instruction (to from the FPCR, FPSR, or FPIAR) and the move multiple data registers
(FMOVEN) instruction cannot generate floating-point exceptions ; therefore, these instructions do not modify the FPIAR. Thus,
the FMOVE and FMOVEM instructions can be used to read the FPIAR in the trap handler without changing the previous
value.
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