TS68040 ATMEL Corporation, TS68040 Datasheet - Page 27

• Manufacturer Part Number: TS68040
• Description: 32-bit Mpu, 25-33 MHZ
• Manufacturer: ATMEL Corporation

Single- and double-precision floating-point data formats are implemented in the FPU as defined by the IEEE standard. These
data formats are the main floating-point formats and should be used for most calculations involving real numbers.
The extended-precision data format is also in conformance with the IEEE standard, but the standard does not specify this
format to the bit level as it does for single- and double-precision. The memory format for the FPU consists of 96 bits (three
long words). Only 80 bits are actually used ; the other 16 bits are reserved for future use and for long-word alignment of
the floating-point data structures in memory. The extended-precision format has a 15-bit exponent, a 64-bit mantissa, and a
1-bit mantissa sign. Extended-precision numbers are intended for use as temporary variables, intermediate values, or where
extra precision is needed.
The TS 68040 addressing modes are shown in Table 19. The register indirect addressing modes support post-increment,
predecrement, offset, and indexing, which are particularly useful for handling data structures common to sophisticated ap-
plications and high-level languages. The program counter indirect mode also has indexing and offset capabilities ; this ad-
dressing mode is typically required to support position-independent software. In addition to these addressing modes, the
TS 68040 provides index sizing and scaling features that enhance software performance. Data formats are supported ortho-
gonally by all arithmetic operations and by all appropriate addressing modes.
Table 19 - Addressing modes
Notes :
Register direct
Register indirect
Register indirect with index
Memory indirect
Program counter indirect with displacement
Program counter indirect with index
Program counter memory indirect
Absolute
Immediate
Date register direct
Address register direct
Address register indirect
Address register indirect with postincrement
Address register indirect with predecrement
Address register indirect with displacement
Address register indirect with index (8-bit displacement)
Address register indirect with index (base displacement)
Memory indirect postincrement
Memory indirect preindexed
PC indirect with index (8-bit displacement)
PC indirect with index (base displacement
PC memory indirect postindexed
PC memory indirect preindexed
Absolute short
Absolute long
d 8 , d 16 = A twos-complement or sign-extended displacement ; added as part of the effective address calculation ;
(data) = Immediate value of 8, 16 or 32 bits.
DN = Data register, D0-D7
AN = Address register, A0-A7
PC = Program counter.
Xn = Address or data register used as an index register ; form is Xn, SIZE*SCALE, where SIZE is W or L
bd = A twos-complement base displacement ; when present, size can be 16 or 32 bits.
od
( ) = Effective address.
[ ] = Used as indirect address to long-word address.
=
size is 8 (d 8 ) or 16 (d 16 ) bits ; when omitted, assemblers use a value of zero.
(indicates index register size) and SCALE is 1, 2, 4 or 8 (index register os multiplied by SCALE) ; use of
SIZE and or SCALE is optional.
Outer displacement added as part of effective address calculation after any memory indirection ; use is
optional with a size of 16 or 32 bits.
Addressing modes
Dn
An
(An)
(An)
(An)
(d 16 , An)
(d 8 , An, Xn)
(bd, An, Xn)
([bd, An], Xn, od)
([bd, An, Xn], od)
(d 16 , PC)
(d 8 , PC, Xn)
(bd, PC, Xn)
([bd, PC], Xn, od)
([bd, PC, Xn], od)
xxx.W
xxx.L
# (data)
Syntax
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