MD3331-D32-V3Q18 M-Systems Inc., MD3331-D32-V3Q18 Datasheet - Page 39

• Manufacturer Part Number: MD3331-D32-V3Q18
• Description: Mobile Diskonchip Plus 128Mbits 1.8V I/o
• Manufacturer: M-Systems Inc.

Mobile DiskOnChip Plus 16/32MByte 1.8V I/O
8.3.3 Using Mobile DiskOnChip Plus in Asynchronous Boot Mode
Platforms that host CPUs that wake up in burst mode should use Asynchronous Boot mode when using Mobile
DiskOnChip Plus as the system boot device.
During platform initialization, certain CPUs wake up in 32-bit mode and issue instruction fetch cycles continuously.
An XScale CPU, for example, initiates a 16-bit read cycle, but after the first word is read, it continues to hold CE#
and OE# asserted while it increments the address and reads additional data as a burst. A StrongARM CPU wakes up
in 32-bit mode and issues double-word instruction fetch cycles.
Since Mobile DiskOnChip Plus derives its internal clock signal from the CE#, OE# and WE# inputs, it cannot
distinguish between these burst cycles. To support this type of access, Mobile DiskOnChip Plus needs to be set in
Asynchronous Boot mode.
To set Mobile DiskOnChip Plus in Asynchronous Boot mode, set the byte RAM MODE SELECT to 8FH. This can
be done through the Mobile DiskOnChip Plus format utility or by customizing the IPL code. For more information
on the format utility, refer to the DiskOnChip Software Utilities user manual or the TrueFFS Software Development
Kit (SDK) developer guide. For further details on customizing the IPL code, refer to application note AP-DOC-044,
Writing an IPL for DiskOnChip Plus 16MByte.
Once in Asynchronous Boot mode, the CPU can fetch its instruction cycles from the Mobile DiskOnChip Plus
Programmable Boot Block. After reading from this block and completing boot, Mobile DiskOnChip Plus returns to
derive its internal clock signal from the CE#, OE# and WE# inputs. Please refer to Section 10.4 for read timing
specifications for Asynchronous Boot mode.
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Data Sheet, Rev. 1.7
95-SR-000-10-8L