MD3331-D32-V3Q18 M-Systems Inc., MD3331-D32-V3Q18 Datasheet - Page 35

• Manufacturer Part Number: MD3331-D32-V3Q18
• Description: Mobile Diskonchip Plus 128Mbits 1.8V I/o
• Manufacturer: M-Systems Inc.

7.9
Description:
Address (hex):
Type:
Reset Value:
Note: For further information on the Output Control and Protection Status registers, refer to the addendum to this
7.10 Interrupt Control
Description:
Address (hex):
Type:
Reset Value:
35
0-2, 4-7
Bit No.
Bit No.
RFU_0
Bit 7
Bit 7
0-2
3
3
4
5
Output Control Register
data sheet, Mobile DiskOnChip Plus/DIMM Plus Register Description.
Reserved for future use.
SLOCK [Sticky Lock]. Setting this bit to a 1 has the same effect as asserting the LOCK# input, up
until the next power-up or reset. Once set, this bit can only be cleared by asserting the RSTIN#
input. Like the LOCK# input, the assertion of this bit prevents the protection key from disabling the
protection for a given partition if the value of the LOCK bit in its respective Data Protect Structure is
set. When read, this bit always returns the value 0. Setting this bit affects the state of the LOCK# bit
in the Protection Status register.
FRDY_T[2:0] (Flash Ready Trigger). This field determines if an interrupt will be generated when the
flash array of Mobile DiskOnChip Plus is ready, as follows:
000: Interrupts are disabled – Holds the IRQ# output in the negated state.
001: Interrupt when flash array is ready.
PROT_T (Protection Trigger). When set, an interrupt is generated upon a data protection violation.
EDGE (Edge-sensitive interrupt)
0: Specifies level-sensitive interrupts in which the IRQ# output remains asserted until the interrupt
is cleared.
1: Specifies edge-sensitive interrupts in which the IRQ# output pulses low.
IRQ_F: (Interrupt Request when flash array is ready) Indicates that the IRQ# output has been
asserted due to an indication that the flash array is ready. Writing 1 to this bit clears its value,
This register controls the behavior of certain output balls.
100C
Read/Write
01H
Interrupts may be generated when the flash transitions from the busy state to the ready state, or by
a data protection violation.
100E
Read/Write
00H
IRQ_P
Bit 6
Bit 6
RFU_0
IRQ_F
Bit 5
Bit 5
Data Sheet, Rev. 1.7
EDGE
Bit 4
Bit 4
Description
Description
PROT_T
SLOCK
Bit 3
Bit 3
Mobile DiskOnChip Plus 16/32MByte 1.8V I/O
RFU_1
Bit 2
Bit 2
FRDY_T[2:0
RFU_0
Bit 1
Bit 1
95-SR-000-10-8L
RFU_1
Bit 0
Bit 0