MPC8323E Freescale Semiconductor, MPC8323E Datasheet - Page 9

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MPC8323E

Manufacturer Part Number
MPC8323E
Description
Integrated Communications Processor Family Hardware Specifications
Manufacturer
Freescale Semiconductor
Datasheet

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2.1.4
Table 4
2.2
MPC8323E does not require the core supply voltage and I/O supply voltages to be applied in any particular
order. However, note that during the power ramp up, before the power supplies are stable, there might be
a period of time that I/O pins are actively driven. After the power is stable, as long as PORESET is
asserted, most I/O pins are three-stated. In order to minimize the time that I/O pins being actively driven,
it is recommended to apply core voltage before I/O voltage and assert PORESET before the power supplies
fully ramp up. The core voltage (V
GV
after the core voltage has reached its nominal level (see
observed if these recommendations are not followed.
Freescale Semiconductor
Input capacitance for all pins except CLKIN
Input capacitance for CLKIN
Note:
1. The external clock generator should be able to drive 10 pF.
MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
DD
) reaches 0.7 V. In addition, the I/O voltage should reach its nominal level within 100 microseconds
describes the input capacitance for the CLKIN pin in the MPC8323E.
Power Sequencing
Input Capacitance Specification
0.7 V
V
Parameter/Condition
0
Table 4. Input Capacitance Specification
Figure 4. MPC8323E Power Sequencing
Min
DD
) should reach its nominal level before the I/O voltage (OV
100 μs
Max
Symbol
C
ICLKIN
Figure
C
I/O Voltage (GV
I
4). Excessive current consumption may be
Min
10
6
DD
Core Voltage (V
and OV
Max
DD
8
) 3.3 V
DD
Electrical Characteristics
) 1 V
t
Unit
pF
pF
DD
Notes
1
and
9

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