MPC8323E Freescale Semiconductor, MPC8323E Datasheet - Page 13

• Manufacturer Part Number: MPC8323E
• Description: Integrated Communications Processor Family Hardware Specifications
• Manufacturer: Freescale Semiconductor

Output high voltage
Output low voltage
Output low voltage
Input high voltage
Input low voltage
Input current
Note:
1. This specification applies when operating from 3.3 V supply.
5.1
Table 11
6
This section describes the DC and AC electrical specifications for the DDR1 and DDR2 SDRAM interface
of the MPC8323E. Note that DDR1 SDRAM is Dn_GV
Dn_GV
6.1
Table 12
MPC8323E when Dn_GV
Freescale Semiconductor
I/O supply voltage
I/O reference voltage
I/O termination voltage
Input high voltage
Input low voltage
Output leakage current
Output high current (V
Output low current (V
Notes:
1. D n
2. MVREF n
3. V
4. Output leakage is measured with all outputs disabled, 0 V
Peak-to-peak noise on MVREF n
equal to MVREF n
MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
TT
_
GV
is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
Parameter/Condition
DDR1 and DDR2 SDRAM
DD
DD
provides the DC electrical characteristics for the MPC8323E reset signals mentioned in
provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
Characteristic
Reset Signals DC Electrical Characteristics
DDR1 and DDR2 SDRAM DC Electrical Characteristics
REF
(typ) = 1.8 V. The AC electrical specifications are the same for DDR1 and DDR2 SDRAM.
is expected to be within 50 mV of the DRAM D n
Table 12. DDR2 SDRAM DC Electrical Characteristics for D n
is expected to be equal to 0.5 × D n
REF
OUT
OUT
. This rail should track variations in the DC level of MVREF n
= 0.280 V)
= 1.35 V)
DD
Table 11. Reset Signals DC Electrical Characteristics
(typ) = 1.8 V
REF
MVREF n
may not exceed ±2% of the DC value.
D n
Symbol
Symbol
V
V
V
V
V
_
I
V
V
I
OH
OL
IN
V
I
I
OL
IH
IL
OZ
OH
OL
GV
TT
IH
IL
DD
REF
.
_
GV
0 V ≤ V
I
OH
I
DD
I
OL
MVREF n
OL
Condition
MVREF n
0.49 × D n
, and to track D n
= –6.0 mA
= 3.2 mA
= 6.0 mA
IN
—
—
≤
_
GV
V
≤ OV
–13.4
1.71
–0.3
–9.9
13.4
OUT
Min
REF
REF
DD
DD
_
DD
≤
GV
at all times.
+ 0.125
– 0.04
(typ) = 2.5 V and DDR2 SDRAM is
D n
DD
_
_
GV
GV
DD
–0.3
Min
DD
2.4
2.0
—
—
—
.
MVREF n
MVREF n
DC variations as measured at the receiver.
0.51 × D n
REF
D n
_
.
_
GV
GV
Max
1.89
REF
9.9
—
—
REF
OV
DD
DD
_
GV
DD
+ 0.3
Max
– 0.125
+ 0.04
0.5
0.4
0.8
(typ) = 1.8 V
±5
—
DD
+ 0.3
DDR1 and DDR2 SDRAM
Unit
mA
mA
μA
Unit
V
V
V
V
V
μA
V
V
V
V
V
Table
Notes
Notes
1
2
3
4
1
1
1
1
13
9.