MPC8323E Freescale Semiconductor, MPC8323E Datasheet
MPC8323E
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MPC8323E Summary of contents
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... MPC8323, MPC8321E, and MPC8321. To locate published errata or updates for this document, refer to the MPC8323E product summary page on our website listed on the back cover of this document or, contact your local Freescale sales office. This document contains information on a new product. Specifications and information herein are subject to change without notice. © ...
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... Kbytes of L1 instruction and data caches, dual integer units, and on-chip memory management units (MMUs). The e300c2 core does not contain a Floating Point Unit (FPU). The MPC8323E also includes a 32-bit PCI controller, four DMA channels, a security engine, and a 32-bit DDR1/DDR2 memory controller. ...
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... High-performance, low-power, and cost-effective single-chip data plane/control plane solution for ATM or IP/Ethernet packet processing (or both). • MPC8323E QUICC Engine block offers a future-proof solution for next generation designs by supporting programmable protocol termination and network interface termination to meet evolving protocol standards. • ...
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... Serial Interfaces The MPC8323E serial interfaces are as follows: • Support for one UL2 interface with 31 multi-PHY addresses (MPC8323E and MPC8323 only) • Support for up to three 10/100 Mbps Ethernet interfaces using MII or RMII • Support for up to four T1/E1/J1/E3 or DS-3 serial interfaces (TDM) • ...
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... The PIC programming model is compatible with the MPC8260 interrupt controller, and it supports 8 external and 35 internal discrete interrupt sources. Interrupts can also be redirected to an external interrupt controller. MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Overview ...
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... Electrical Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the MPC8323E. The MPC8323E is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications. ...
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... Power Supply Voltage Specification Table 2 provides the recommended operating conditions for the MPC8323E. Note that these values are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 2. Recommended Operating Conditions Characteristic Core supply voltage PLL supply voltage ...
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... Electrical Characteristics Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8323E for the 3.3-V signals, respectively. Overvoltage Waveform Undervoltage Waveform Figure 3. Maximum AC Waveforms on PCI Interface for 3.3-V Signaling 2.1.3 Output Driver Characteristics Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates ...
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... Power Sequencing MPC8323E does not require the core supply voltage and I/O supply voltages to be applied in any particular order. However, note that during the power ramp up, before the power supplies are stable, there might be a period of time that I/O pins are actively driven. After the power is stable, as long as PORESET is asserted, most I/O pins are three-stated ...
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... Power Characteristics 3 Power Characteristics The estimated typical power dissipation for this family of MPC8323E devices is shown in CSB QUICC Engine Frequency (MHz) Frequency (MHz) 133 200 133 200 Notes: 1. The values do not include I/O supply power (OV 2. Typical power is based on a nominal voltage of V benchmark application. The measurements were taken on the MPC8323MDS evaluation board using WC process silicon. ...
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... CLKIN input current PCI_SYNC_IN input current PCI_SYNC_IN input current 4.2 AC Electrical Characteristics The primary clock source for the MPC8323E can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. (CLKIN/PCI_CLK) AC timing specifications for the MPC8323E. Parameter/Condition CLKIN/PCI_CLK frequency ...
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... MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Reference Manual for more details the clock period of the input clock applied to CLKIN only valid when the MPC8323E is in PCI host mode. See CLKIN the MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Reference Manual for more details. ...
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... Reset Signals DC Electrical Characteristics Table 11 provides the DC electrical characteristics for the MPC8323E reset signals mentioned in Table 11. Reset Signals DC Electrical Characteristics Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current Note: 1. This specification applies when operating from 3.3 V supply. ...
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... Parameter/Condition Input/output capacitance: DQ,DQS Delta input/output capacitance: DQ, DQS Note This parameter is sampled (peak-to-peak) = 0.2 V. OUT MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev (typ Symbol DIO = 1.8 V ± 0.090 MHz 25°C, V ...
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... AC timing specifications for the DDR1 and DDR2 SDRAM interfaces. Table 19. DDR1 and DDR2 SDRAM Output AC Timing Specifications At recommended operating conditions with D n _GV Parameter MCK cycle time, (MCK/MCK crossing) MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor of 1.8 ± 5%. DD Symbol ...
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... CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Reference Manual for a description and understanding of the timing modifications enabled by use of these bits. ...
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... DDR1 and DDR2 SDRAM output timing diagram. MCK[n] MCK[n] ADDR/CMD Write A0 t DDKHMP MDQS[n] MDQ[x] Figure 6. DDR1 and DDR2 SDRAM Output Timing Diagram MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor MCK MCK t MCK t (max) = 0.6 ns DDKHMH t (min) = – ...
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... Ethernet Controller (10/100 Mbps)—MII/RMII Electrical Characteristics The electrical characteristics specified here apply to all MII (media independent interface) and RMII (reduced media independent interface), except MDIO (management data input/output) and MDC MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev Symbol V ...
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... TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay TX_CLK data clock rise V (min MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Symbol Conditions OV — DD ...
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... RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise V (min (max MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev 3.3 V ± 10 Symbol (min ...
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... MII receive AC timing diagram. RX_CLK RXD[3:0] RX_DV RX_ER 8.2.2 RMII AC Timing Specifications This section describes the RMII transmit and receive AC timing specifications. MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor of 3.3 V ± 10 Symbol (min) t ...
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... REF_CLK clock period REF_CLK duty cycle RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK REF_CLK clock rise V (min (max MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev 3.3 V ± 10 Symbol t RMX t ...
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... The electrical characteristics specified here apply to MII management interface signals MDIO (management data input/output) and MDC (management data clock). The electrical characteristics for MII, and RMII are specified in Characteristics.” MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor of 3.3 V ± 10%. DD ...
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... For rise and fall times, the latter MDC convention is used with the appropriate letter: R (rise (fall). MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev Table 27. ...
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... Low-level output voltage Input current 9.2 Local Bus AC Electrical Specifications Table 30 describes the general timing parameters of the local bus interface of the MPC8323E. Table 30. Local Bus General Timing Parameters Parameter Local bus cycle time Input setup to local bus clock Input hold from local bus clock LALE output fall to LAD output transition (LATCH hold time) MPC8323E PowerQUICC™ ...
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... For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Figure 14 provides the AC test load for the local bus. Output MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev Symbol t ...
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... LCS[0:3]/LWE UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:15]/LDP[0:3] UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] Figure 16. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor t LBIVKH t LBKHOV t LBKHOZ ...
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... DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the MPC8323E. Table 31. JTAG Interface DC Electrical Characteristics Characteristic Output high voltage Output low voltage Output low voltage Input high voltage MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev LBKHOZ t LBKHOV t LBIVKH ...
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... TRST assert time Input setup times: Boundary-scan data Input hold times: Boundary-scan data Valid times: Boundary-scan data Output hold times: Boundary-scan data MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Symbol Condition V — ≤ V ≤ OV ...
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... Non-JTAG signal input timing with respect Non-JTAG signal output timing with respect Guaranteed by design and characterization. Figure 18 provides the AC test load for TDO and the boundary-scan outputs of the MPC8323E. Output Figure 18. AC Test Load for the JTAG Interface Figure 19 provides the JTAG clock input timing diagram ...
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... JTAG External Clock TDI, TMS t JTKLOX TDO TDO Output Data Valid Figure 22. Test Access Port Timing Diagram MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor VM t JTDVKH t JTKLDV t JTKLDZ VM = Midpoint Voltage (OV DD /2) Figure 21 ...
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... Output voltage (open drain or open collector) condition = 3 mA sink current capacitance of one bus line in pF Refer to the MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Reference Manual for information on the digital filter used. 4. I/O pins will obstruct the SDA and SCL lines ...
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... For rise and fall times, the latter convention is used with the appropriate letter: R (rise (fall). 2. MPC8323E provides a hold time of at least 300 ns for the SDA signal (referred to the V the undefined region of the falling edge of SCL. ...
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... Ranges listed do not meet the full range of the DC specifications of the PCI 2.3 Local Bus Specifications. 12.2 PCI AC Electrical Specifications This section describes the general AC timing parameters of the PCI bus of the MPC8323E. Note that the PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8323E is configured as a host or agent device. ...
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... Input timings are measured at the pin. Figure 25 provides the AC test load for PCI. Output Figure 26 shows the PCI input AC timing conditions. CLK Input Figure 26. PCI Input AC Timing Measurement Conditions MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 1 Symbol Min t — PCKHOV 2 ...
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... Output Delay High-Impedance Output Figure 27. PCI Output AC Timing Measurement Condition 13 Timers This section describes the DC and AC electrical specifications for the timers of the MPC8323E. 13.1 Timer DC Electrical Characteristics Table 38 provides the DC electrical characteristics for the MPC8323E timer pins, including TIN, TOUT, TGATE, and RTC_CLK. ...
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... Figure 28 provides the AC test load for the timers. Output 14 GPIO This section describes the DC and AC electrical specifications for the GPIO of the MPC8323E. 14.1 GPIO DC Electrical Characteristics Table 11 provides the DC electrical characteristics for the MPC8323E GPIO. Table 40. GPIO DC Electrical Characteristics Characteristic Output high voltage ...
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... This section describes the DC and AC electrical specifications for the external interrupt pins of the MPC8323E. 15.1 IPIC DC Electrical Characteristics Table 42 provides the DC electrical characteristics for the external interrupt pins of the MPC8323E. Table 42. IPIC DC Electrical Characteristics Characteristic Input high voltage Input low voltage Input current ...
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... SPI This section describes the DC and AC electrical specifications for the SPI of the MPC8323E. 16.1 SPI DC Electrical Characteristics Table 44 provides the DC electrical characteristics for the MPC8323E SPI. Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current 16 ...
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... DC electrical characteristics for the MPC8323E TDM/SI. Table 46. TDM/SI DC Electrical Characteristics Characteristic Output high voltage Output low voltage Input high voltage MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev Table 45. Note that although the specifications t NEIXKH ...
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... Input Signals: TDM/SI (See Note) Output Signals: TDM/SI (See Note) Note: The clock edge is selectable on TDM/SI. Figure 34. TDM/SI AC Timing (External Clock) Diagram MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Symbol Condition V — ≤ V ≤ OV ...
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... UTOPIA 18 UTOPIA This section describes the UTOPIA DC and AC electrical specifications of the MPC8323E. The MPC8321E and MPC8321 do not support UTOPIA. 18.1 UTOPIA DC Electrical Characteristics Table 48 provides the DC electrical characteristics for the MPC8323E UTOPIA. Table 48. UTOPIA DC Electrical Characteristics Characteristic Output high voltage Output low voltage ...
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... This section describes the DC and AC electrical specifications for the high level data link control (HDLC), BISYNC, transparent, and synchronous UART of the MPC8323E. MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor HDLC, BISYNC, Transparent, and Synchronous UART = 50 Ω ...
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... The symbols used for timing specifications follow the pattern of t inputs and t (first two letters of functional block)(reference)(state)(signal)(state) internal timing (HI) for the time t serial MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev Symbol Condition – ...
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... HEIVKH Input Signals: (See Note) Output Signals: (See Note) Note: The clock edge is selectable. Figure 39. AC Timing (External Clock) Diagram MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor HDLC, BISYNC, Transparent, and Synchronous UART Symbol t UAIKHOV t ...
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... Output Signals: (See Note) Note: The clock edge is selectable. Figure 40. AC Timing (Internal Clock) Diagram 20 USB This section provides the AC and DC electrical specifications for the USB interface of the MPC8323E. 20.1 USB DC Electrical Characteristics Table 53 provides the DC electrical characteristics for the USB interface. ...
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... Figure 41 provide the AC test load for the USB. Output 21 Package and Pin Listings This section details package parameters, pin assignments, and dimensions. The MPC8323E is available in a thermally enhanced Plastic Ball Grid Array (PBGA); see MPC8323E PBGA,” and Section 21.2, “Mechanical Dimensions of the MPC8323E PBGA,” ...
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... Maximum solder ball diameter measured parallel to datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. Figure 42. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8323E PBGA MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev Freescale Semiconductor ...
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... MEMC_MDQ19 MEMC_MDQ20 MEMC_MDQ21 MEMC_MDQ22 MEMC_MDQ23 MEMC_MDQ24 MEMC_MDQ25 MEMC_MDQ26 MEMC_MDQ27 MEMC_MDQ28 MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Table 55. MPC8323E PBGA Pinout Listing Package Pin Number DDR Memory Controller Interface AE9 AD10 AF10 AF9 AF7 AE10 ...
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... MEMC_MA1 MEMC_MA2 MEMC_MA3 MEMC_MA4 MEMC_MA5 MEMC_MA6 MEMC_MA7 MEMC_MA8 MEMC_MA9 MEMC_MA10 MEMC_MA11 MEMC_MA12 MEMC_MA13 MEMC_MWE MEMC_MRAS MEMC_MCAS MEMC_MCS MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev Package Pin Number Pin Type AD20 IO AF23 IO AD22 IO AC9 O AD5 O AE20 O AE22 ...
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... RST_LAD15/LAD15 RST_LA16/LA16 RST_LA17/LA17 RST_LA18/LA18 RST_LA19/LA19 RST_LA20/LA20 RST_LA21/LA21 RST_LA22/LA22 RST_LA23/LA23 RST_LA24/LA24 RST_LA25/LA25 RST_LCS0/LCS0 MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Package Pin Number AD14 AF14 AE14 AF11 Local Bus Controller Interface N25 P26 P25 R26 R25 ...
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... UART_CTS1/MSRCID2 (DDR ID)/LSRCID2 UART_RTS1/MSRCID3 (DDR ID)/LSRCID3 UART_SOUT2/MSRCID4 (DDR ID)/LSRCID4 UART_SIN2/MDVAL (DDR ID)/LDVAL UART_CTS2 UART_RTS2 IIC_SDA/CKSTOP_OUT IIC_SCL/CKSTOP_IN MCP_OUT IRQ0/MCP_IN IRQ1 MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev Package Pin Number AB25 AA23 AA24 Y23 W25 V25 V24 L23 ...
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... TEST_MODE QUIESCE HRESET PORESET SRESET CLKIN CLKIN PCI_SYNC_OUT RTC_PIT_CLOCK PCI_SYNC_IN/PCI_CLK PCI_CLK0/clkpd_cerisc1_ipg_clkout/DPTC_OSC PCI_CLK1/clkpd_half_cemb4ucc1_ipg_clkout/ CLOCK_XLB_CLOCK_OUT PCI_CLK2/clkpd_third_cesog_ipg_clkout/ cecl_ipg_ce_clock MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Package Pin Number Pin Type AE26 AE25 AF25 F1 M23 JTAG W26 Y26 ...
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... PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14/ECID_TMODE_IN PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev Package Pin Number Power and Ground Supplies P3 AA1 AB15 C24 AB8 AB17 PCI AF2 AE2 L1 ...
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... PCI_PAR PCI_FRAME PCI_TRDY PCI_IRDY PCI_STOP PCI_DEVSEL PCI_IDSEL PCI_SERR PCI_PERR PCI_REQ0 PCI_REQ1/CPCI_HS_ES PCI_REQ2 PCI_GNT0 PCI_GNT1/CPCI_HS_LED PCI_GNT2/CPCI_HS_ENUM M66EN MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Package Pin Number Pin Type AB2 AC1 IO AA3 IO AA4 IO AD1 IO AD2 ...
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... TDMB_TXD[3]/LA5 (LBIU) GPIO_PA22/Enet2_RXD[0]/SER2_RXD[0]/ TDMB_RXD[0]/LA6 (LBIU) GPIO_PA23/Enet2_RXD[1]/SER2_RXD[1]/ TDMB_RXD[1]/LA7 (LBIU) GPIO_PA24/Enet2_RXD[2]/SER2_RXD[2]/ TDMB_RXD[2]/LA8 (LBIU) GPIO_PA25/Enet2_RXD[3]/SER2_RXD[3]/ TDMB_RXD[3]/LA9 (LBIU) MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev Package Pin Number Pin Type CE/GPIO ...
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... GPIO_PB7/Enet3_RXD[3]/SER3_RXD[3]/ TDMC_RXD[3] GPIO_PB8/Enet3_RX_ER/SER3_CD/TDMC_REQ GPIO_PB9/Enet3_TX_ER/TDMC_CLKO GPIO_PB10/Enet3_RX_DV/SER3_CTS/ TDMC_RSYNC GPIO_PB11/Enet3_COL/RXD[4]/SER3_RXD[4]/ TDMC_STROBE GPIO_PB12/Enet3_TX_EN/SER3_RTS/ TDMC_TSYNC GPIO_PB13/Enet3_CRS/SDET GPIO_PB14/CLK12 GPIO_PB15 UPC1_TxADDR[4] GPIO_PB16 UPC1_RxADDR[4] MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Package Pin Number Pin Type E26 IO F25 IO E25 IO J25 IO F26 IO ...
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... GPIO_PB30/Enet4_TX_EN/SER4_RTS/ TDMD_TSYNC GPIO_PB31/Enet4_CRS/SDET GPIO_PC0/UPC1_TxDATA[0]/SER5_TXD[0] GPIO_PC1/UPC1_TxDATA[1]/SER5_TXD[1] GPIO_PC2/UPC1_TxDATA[2]/SER5_TXD[2] GPIO_PC3/UPC1_TxDATA[3]/SER5_TXD[3] GPIO_PC4/UPC1_TxDATA[4] GPIO_PC5/UPC1_TxDATA[5] GPIO_PC6/UPC1_TxDATA[6] GPIO_PC7/UPC1_TxDATA[7] GPIO_PC8/UPC1_RxDATA[0]/SER5_RXD[0] GPIO_PC9/UPC1_RxDATA[1]/SER5_RXD[1] MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev Package Pin Number Pin Type D10 IO C10 ...
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... GPIO_PC26/UPC1_RxPRTY/CE_EXT_REQ2 GPIO_PC27/UPC1_RxEN GPIO_PC28/UPC1_TxSOC GPIO_PC29/UPC1_TxCLAV/SER5_CTS GPIO_PC30/UPC1_TxPRTY GPIO_PC31/UPC1_TxEN/SER5_RTS GPIO_PD0/SPIMOSI/CE_TRB_PIN5 GPIO_PD1/SPIMISO/CE_TRB_PIN6 GPIO_PD2/SPICLK/CE_TRB_PIN7 GPIO_PD3/SPISEL/CE_TRB_PIN8 GPIO_PD4/SPI_MDIO/CE_MUX_MDIO GPIO_PD5/SPI_MDC/CE_MUX_MDC GPIO_PD6/CLK8/BRGO16/CE_EXT_REQ3 GPIO_PD7/GTM1_TIN1/GTM2_TIN2/CLK5 GPIO_PD8/GTM1_TGATE1/GTM2_TGATE2/CLK6 GPIO_PD9/GTM1_TOUT1/CE_PIO25 MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Package Pin Number Pin Type B21 IO A20 IO D19 IO C18 IO D18 IO A25 IO C21 ...
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... CE_PIO24 GPIO_PD19/CE_RISC1_INT/CE_EXT_REQ4/ CE_PIO26 GPIO_PD20/CLK18/BRGO6 GPIO_PD21/CLK16/BRGO5/UPC1_CLKO GPIO_PD22/CLK4/BRGO9/UCC2_CLKO GPIO_PD23/CLK3/BRGO10/UCC3_CLKO GPIO_PD24/CLK10/BRGO2/UCC4_CLKO GPIO_PD25/CLK13/BRGO16/UCC5_CLKO GPIO_PD26/CLK2/BRGO4/UCC1_CLKO GPIO_PD27/CLK1/BRGO3 GPIO_PD28/CLK19/BRGO11 GPIO_PD29/CLK15/BRGO8 GPIO_PD30/CLK14 GPIO_PD31/CLK7/BRGO15 GV DD MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev Package Pin Number J24 B25 D21 C19 A7 B7 A12 ...
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... These JTAG and local bus pins have weak internal pull-up P-FETs that are always enabled. 5. This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI specifications recommendation. 6. This pin must always be tied to GND. MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Package Pin Number ...
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... Clocking in PCI Host Mode When the MPC8323E is configured as a PCI host device (RCWH[PCIHOST] = 1), CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the PCI_SYNC_OUT and PCI_CLK_OUT MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 ...
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... OCCR[PCICOEn] bit. All output clocks are phase-aligned to each other. 22.2 Clocking in PCI Agent Mode When the MPC8323E is configured as a PCI agent device, PCI_CLK is the primary input clock. In agent mode, the CLKIN signal should be tied to GND, and the clock output signals, PCI_CLK_OUTn and PCI_SYNC_OUT, are not used. ...
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... LBC clock divider to create the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LBC clock divider ratio is controlled by LCCR[CLKDIV]. See the “LBC Bus Clock and Clock Ratios” section in the MPC8323E PowerQUICC™ II Pro Communications Processor Reference Manual for more information. ...
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... PCI_CLK) and the internal coherent system bus clock (csb_clk). shows the expected frequency values for the CSB frequency for select csb_clk to CLKIN/PCI_SYNC_IN ratios. MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Table 58. System PLL Multiplication Factors ...
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... CFG_CLKIN_DIV_B is only used for host mode; CLKIN must be tied low and CFG_CLKIN_DIV_B must be pulled up (high) in agent mode. 2 CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode. MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev Table 59. CSB Frequency Options Input Clock Frequency (MHz) ...
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... Core VCO frequency = core frequency × VCO divider VCO divider (RCWL[COREPLL[0:1]]) must be set properly so that the core VCO frequency is in the range of 500–800 MHz. MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor shows the encodings for RCWL[COREPLL]. COREPLL values not listed Table 60 ...
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... The QUICC Engine VCO frequency is derived from the following equations: ce_clk = (primary clock input × CEPMF) ÷ CEPDF) QUICC Engine VCO Frequency = ce_clk × VCO divider × CEPDF) MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev QUICC Engine PLL Multiplication RCWL[CEPDF] ...
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... Thermal This section describes the thermal specifications of the MPC8323E. 23.1 Thermal Characteristics provides the package thermal characteristics for the 516 27 × PBGA of the MPC8323E. Table 64 Table 64. Package Thermal Characteristics for PBGA Characteristic Junction-to-ambient natural convection Junction-to-ambient natural convection ...
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... The thermal performance of any component is strongly dependent on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev Board type Natural convection × ...
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... When a heat sink is used, the thermal resistance is expressed as the sum of a junction-to-case thermal resistance and a case to ambient thermal resistance θ θ θ MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor ) D ) can be used to determine the junction temperature with Thermal ...
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... San Jose, CA 95112 Internet: www.mei-thermal.com Tyco Electronics Chip Coolers™ P.O. Box 3668 Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev For instance, the user can change the size of the heat θ CA 603-224-9988 408-567-8082 ...
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... Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 603-635-5102 ...
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... Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor. MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev ...
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... Decoupling Recommendations Due to large address and data buses, and high operating frequencies, the MPC8323E can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8323E system, and the MPC8323E itself requires a clean, tightly regulated source of power ...
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... Local Bus, Ethernet, DUART, Impedance Control, Configuration, Power Management Differential Note: Nominal supply voltages. See MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev trimmed until the voltage at the pad equals P )/ Pad Data ...
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... Configuration Pin Multiplexing The MPC8323E provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration pins). These pins are generally used as output only pins in normal operation. ...
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... Part Numbers Fully Addressed by This Document Table 67 provides the Freescale part numbering nomenclature for the MPC8323E family. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the maximum processor core frequency, the part numbering scheme also includes the maximum effective DDR memory speed and QUICC Engine bus frequency ...
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... Part Marking Parts are marked as in the example shown in Figure 46. Freescale Part Marking for PBGA Devices MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor Figure 46. MPCnnnnetppaaar core/platform MHZ ATWLYYWW CCCCC *MMMMM YWWLAZ PBGA Notes : ATWLYYWW is the traceability code. ...
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... Denver, Colorado 80217 +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC8323EEC Rev. 0 06/2007 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...