MPC8323E Freescale Semiconductor, MPC8323E Datasheet - Page 69

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MPC8323E

Manufacturer Part Number
MPC8323E
Description
Integrated Communications Processor Family Hardware Specifications
Manufacturer
Freescale Semiconductor
Datasheet

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22.7
To simplify the PLL configurations, the MPC8323E might be separated into two clock domains. The first
domain contain the CSB PLL and the core PLL. The core PLL is connected serially to the CSB PLL, and
has the csb_clk as its input clock. The second clock domain has the QUICC Engine PLL. The clock
domains are independent, and each of their PLLs are configured separately. Both of the domains has one
common input clock.
23 Thermal
This section describes the thermal specifications of the MPC8323E.
23.1
Table 64
Freescale Semiconductor
Junction-to-ambient natural convection
Junction-to-ambient natural convection
Junction-to-ambient (@200 ft/min)
Junction-to-ambient (@200 ft/min)
Junction-to-board
Junction-to-case
MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Conf No.
1
2
3
4
5
6
provides the package thermal characteristics for the 516 27 × 27 mm PBGA of the MPC8323E.
Suggested PLL Configurations
Thermal Characteristics
Characteristic
SPMF
0100
0100
0010
0100
0101
0010
Table 63
0000100
0000101
0000100
0000101
0000101
0000101
Core
Table 64. Package Thermal Characteristics for PBGA
PLL
shows suggested PLL configurations for 33, 25, and 66 MHz input clocks.
Table 63. Suggested PLL Configurations
CEMF
0110
1000
0011
0110
1000
0011
Four-layer board (2s2p)
Four-layer board (2s2p)
Single-layer board (1s)
Single-layer board (1s)
CEDF
Board type
0
0
0
0
0
0
Input Clock
Frequency
(MHz)
33.33
66.67
33.33
66.67
25
25
Frequency
133.33
133.33
133.33
133.33
Symbol
(MHz)
CSB
R
R
100
125
R
R
R
R
θJMA
θJMA
θJC
θJA
θJA
θJB
Frequency
266.66
266.66
333.33
333.33
(MHz)
Value
312.5
Core
250
28
21
23
18
13
9
Frequency
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Unit
Engine
QUICC
(MHz)
200
200
200
200
200
200
1, 2 ,3
Notes
Thermal
1, 2
1, 3
1, 3
4
5
69

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