MPC8323E Freescale Semiconductor, MPC8323E Datasheet - Page 11

• Manufacturer Part Number: MPC8323E
• Description: Integrated Communications Processor Family Hardware Specifications
• Manufacturer: Freescale Semiconductor

4
This section provides the clock input DC and AC electrical characteristics for the MPC8323E.
4.1
Table 7
4.2
The primary clock source for the MPC8323E can be one of two inputs, CLKIN or PCI_CLK, depending
on whether the device is configured in PCI host or PCI agent mode.
(CLKIN/PCI_CLK) AC timing specifications for the MPC8323E.
Freescale Semiconductor
Input high voltage
Input low voltage
CLKIN input current
PCI_SYNC_IN input current
PCI_SYNC_IN input current
CLKIN/PCI_CLK frequency
CLKIN/PCI_CLK cycle time
CLKIN/PCI_CLK rise and fall time
CLKIN/PCI_CLK duty cycle
CLKIN/PCI_CLK jitter
Notes:
1. Caution: The system, core, security, and QUICC Engine block must not exceed their respective maximum or minimum
2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to
operating frequencies.
allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0
Clock Input Timing
provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8323E.
DC Electrical Characteristics
AC Electrical Characteristics
Parameter
Parameter/Condition
AV
conditions and ambient temperature).
DD
n (1.0 V) is estimated to consume 0.05 W (under normal operating
Table 7. CLKIN DC Electrical Characteristics
OV
0.5 V ≤ V
Table 8. CLKIN AC Timing Specifications
DD
0 V ≤ V
0 V ≤ V
– 0.5 V ≤ V
Condition
IN
IN
≤ OV
IN
—
—
≤ 0.5 V or
t
≤ OV
KHK
Symbol
t
DD
KH
f
t
IN
CLKIN
CLKIN
/t
—
, t
DD
≤ OV
– 0.5 V
CLKIN
NOTE
KL
DD
Min
0.6
Symbol
25
15
40
—
V
V
I
I
I
IN
IN
IN
IH
IL
Typical
Table 8
0.8
—
—
—
—
–0.3
Min
2.7
—
—
—
provides the clock input
66.67
±150
Max
1.2
60
—
OV
DD
Max
±50
0.4
±5
±5
MHz
Unit
+ 0.3
Clock Input Timing
ns
ns
ps
%
Notes
Unit
4, 5
μA
μA
μA
—
V
V
1
3
2
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