MT58L128L32P1 Micron Semiconductor Products, Inc., MT58L128L32P1 Datasheet - Page 3

• Manufacturer Part Number: MT58L128L32P1
• Description: 4Mb Syncburst SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Pipelined, Scd,
• Manufacturer: Micron Semiconductor Products, Inc.

GENERAL DESCRIPTION (continued)
(CE#), two additional chip enables for easy depth ex-
pansion (CE2, CE2#), burst control inputs (ADSC#,
ADSP#, ADV#), byte write enables (BWx#) and global
write (GW#).
(OE#), clock (CLK) and snooze enable (ZZ). There is
also a burst mode input (MODE) that selects between
interleaved and linear burst modes. The data-out (Q),
enabled by OE#, is also asynchronous. WRITE cycles
can be from one to two bytes wide (x18) or from one to
four bytes wide (x32/x36), as controlled by the write
control inputs.
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be
internally generated as controlled by the burst advance
input (ADV#).
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa pins and DQPa; BWb# controls DQb
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
Asynchronous inputs include the output enable
Burst operation can be initiated with either address
Address and write control are registered on-chip to
3
PIPELINED, SCD SYNCBURST SRAM
pins and DQPb. During WRITE cycles on the x32 and
x36 devices, BWa# controls DQa pins and DQPa; BWb#
controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. GW#
LOW causes all bytes to be written. Parity bits are only
available on the x18 and x36 versions.
ture during READ cycles. If the device is immediately
deselected after a READ cycle, the output bus goes to a
High-Z state
of clock.
V
compatible. Users can choose either a 3.3V or 2.5V I/O
version. The device is ideally suited for Pentium and
PowerPC pipelined systems and systems that benefit
from a very wide, high-speed data bus. The device is
also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-
wide applications.
sramds) for the latest data sheet.
DD
This device incorporates a single-cycle deselect fea-
Micron’s 4Mb SyncBurst SRAMs operate from a +3.3V
Please refer to Micron’s Web site
4Mb: 256K x 18, 128K x 32/36
power supply, and all inputs and outputs are TTL-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
KQHZ nanoseconds after the rising edge
(www.micron.com/
©2003, Micron Technology, Inc.