MT55L128L32F1 Micron Semiconductor Products, Inc., MT55L128L32F1 Datasheet - Page 9

• Manufacturer Part Number: MT55L128L32F1
• Description: 4Mb ZBT SRAM, 3.3V Vdd, 3.3V or 2.5V I/O, Flow-Through,
• Manufacturer: Micron Semiconductor Products, Inc.

FBGA PIN DESCRIPTIONS
4Mb: 256K x 18, 128K x 32/36 Flow-Through ZBT SRAM
MT55L256L18F1_F.p65 – Rev. F, Pub. 1/03 EN
2A, 2B, 3P, 3R, 2A, 2B, 3P, 3R,
4P, 4R, 8P, 8R, 4P, 4R, 8P, 8R,
10R, 11A, 11R
9P, 9R, 10A,
10B, 10P,
x 1 8
11H
7A
4A
3A
6A
7B
6R
6P
5B
6B
3B
8B
–
–
9P, 9R, 10A,
x32/x36
10B, 10P,
10R, 11R
11H
7A
5A
4A
3A
6A
7B
6R
6P
5B
4B
6B
3B
8B
S Y M B O L T Y P E
OE#(G#)
BWb#
BWd#
BWa#
R/W#
BWc#
CKE#
CE2#
SA0
SA1
CLK
CE#
CE2
SA
ZZ
Input Synchronous Clock Enable: This active LOW input permits CLK
Input Read/Write: This input determines the cycle type when ADV/
Input Synchronous Address Inputs: These inputs are registered and must
Input
Input
Input
Input Synchronous Chip Enable: This active LOW input is used to enable
Input Snooze Enable: This active HIGH, asynchronous input causes the
Input Synchronous Chip Enable: This active HIGH input is used to enable
Input
(continued on next page)
meet the setup and hold times around the rising edge of CLK.
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb. For
the x32 and x36 versions, BWa# controls DQas and DQPa; BWb#
controls DQbs and DQPb; BWc# controls DQcs and DQPc; BWd#
controls DQds and DQPd. Parity is only available on the x18 and x36
versions.
Clock: This signal registers the address, data, chip enable, byte write
enables, and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
Synchronous Chip Enable: This active LOW input is used to enable
the device. CE# is sampled only when a new external address is
loaded. (ADV/LD# LOW)
the device and is sampled only when a new external address is
loaded.
to propagate throughout the device. When CKE# is HIGH, the
device ignores the CLK input and effectively internally extends
the previous CLK cycle. This input must meet setup and hold
times around the rising edge of CLK.
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
LD# is LOW and is the only means for determining READs and
WRITEs. READ cycles may not be converted into WRITEs (and
vice versa) other than by loading a new address. A LOW on this
pin permits BYTE WRITE operations and must meet the setup
and hold times around the rising edge of CLK. Full bus-width
WRITEs occur if all byte write enables are LOW.
the device and is sampled only when a new external address is
loaded.
Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
9
4Mb: 256K x 18, 128K x 32/36
FLOW-THROUGH ZBT SRAM
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D E S C R I P T I O N
©2003, Micron Technology, Inc.