HY27UH088GDM Hynix Semiconductor, HY27UH088GDM Datasheet - Page 48
HY27UH088GDM
Manufacturer Part Number
HY27UH088GDM
Description
8G-Bit NAND Flash Memory
Manufacturer
Hynix Semiconductor
Datasheet
1.HY27UH088GDM.pdf
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Preliminary
HY27UH088G(2/D)M Series
8Gbit (1Gx8bit) NAND Flash
5. APPENDIX : Extra Features
5.1 Automatic Page0 Read after Power Up
The timing diagram related to this operation is shown in Fig. 26
Due to this functionality the CPU can directly download the boot loader from the first page of the NAND flash, storing
it inside the internal cache and starting the execution after the download completed.
5.2 Addressing for program operation
Within a block, the pages must be programmed consecutively from LSB (least significant bit) page of the block to MSB
(most significant bit) page of the block. Random address programming is prohibited. See Fig. 31.
5.3 Stacked Devices Access
A small logic inside the devices allows the possibility to stack up to 4 devices in a single package without changing the
pinout of the memory. To do this the internal address register can store up to 30 addresses(512Mbyte addressing field)
and basing on the 2 MSB pattern each device inside the package can decide if remain active (1 over 4 ) or “hang up”
the connection entering the Stand-By.
Rev 0.5 / Oct. 2005
48
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