HY27UH088GDM Hynix Semiconductor, HY27UH088GDM Datasheet - Page 22

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HY27UH088GDM

Manufacturer Part Number
HY27UH088GDM
Description
8G-Bit NAND Flash Memory
Manufacturer
Hynix Semiconductor
Datasheet
Rev 0.5 / Oct. 2005
CLE Setup time
CLE Hold time
CE# setup time
CE# hold time
WE# pulse width
ALE setup time
ALE hold time
Data setup time
Data hold time
Write Cycle time
WE# High hold time
ALE to Data Loading Time
Data Transfer from Cell to register
ALE to RE# Delay
CLE to RE# Delay
Ready to RE# Low
RE# Pulse Width
WE# High to Busy
Read Cycle Time
RE# Access Time
RE# High to Output High Z
CE# High to Output High Z
RE# or CE# High to Output Hold
RE# High Hold Time
Output High Z to RE# low
CE# Access Time
WE# High to RE# low
Device Resetting Time
(Read / Program / Erase)
Write Protection time
NOTE:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us
2. tADL is the time from the WE# rising edge of final address cycle WE# rising edge of first data cycle.
3. If tCS is less than 10ns tWP must be minimum 35ns, ohterwise, tWP may be minimum 25ns.
4. Program / Erase Enable Operation : tWP# high to tWE# High.
Program / Erase Disable Operation : tWP# Low to tWE# High.
Parameter
Table 12: AC Timing Characteristics
Symbol
tADL
tWW
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WHR
t
t
t
t
CLH
ALH
REA
RHZ
CHZ
REH
t
CEA
RST
CLS
ALS
CLR
WP
WC
WH
t
WB
CH
DS
DH
RR
OH
CS
AR
RP
RC
IR
R
(2)
(4)
8Gbit (1Gx8bit) NAND Flash
HY27UH088G(2/D)M Series
Min
25
100
100
10
10
10
20
10
50
15
10
10
20
25
50
10
15
60
0
0
5
0
(3)
3.3Volt
5/10/500
Max
100
30
30
30
20
45
Preliminary
(1)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
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