MT18LD472 Micron Semiconductor Products, Inc., MT18LD472 Datasheet - Page 15

• Manufacturer Part Number: MT18LD472
• Description: 168-Pin DRAM Dimms, Nonbuffered, (x72), , Status: End of Life (EOL)
• Manufacturer: Micron Semiconductor Products, Inc.

OBSOLETE
NOTES
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate
6. An initial pause of 100 s is required after power-up,
7. AC characteristics assume
8. V
9. In addition to meeting the transition rate specifica-
10. If CAS# = V
11. If CAS# = V
12. Measured with a load equivalent to two TTL gates
13. Requires that
14. Requires that
15. If CAS# is LOW at the falling edge of RAS#, Q will be
16. The
17. The
2, 4 Meg x 72 Nonbuffered DRAM DIMMs
DM60.p65 – Rev. 6/98
are obtained with minimum cycle time and the
outputs open.
cycle time at which proper operation over the full
temperature range is ensured.
followed by eight RAS# REFRESH cycles (RAS#-
ONLY or CBR with WE# HIGH), before proper device
operation is ensured. The eight RAS# cycle wake-ups
should be repeated any time the
requirement is exceeded.
for EDO.
measuring timing of input signals. Transition times
are measured between V
and V
tion, all input signals must transit between V
V
last valid READ cycle.
and 100pF and V
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS# must be
pulsed HIGH for
(MAX) was specified as a reference point only. If
t
limit, then access time was controlled exclusively by
t
without the
always be met.
(MAX) was specified as a reference point only. If
t
limit, then access time was controlled exclusively by
RCD was greater than the specified
CAC (
RAD was greater than the specified
CC
IH
IL
is dependent on output loading. Specified values
(or between V
(MIN) and V
t
t
RCD (MAX) limit is no longer specified.
RAD (MAX) limit is no longer specified.
IH
t
RAC [MIN] no longer applied). With or
).
IH
IL
t
RCD (MAX) limit,
, data output may contain data from the
t
t
, data output is High-Z.
AA and
AA and
IL
OL
t
IL
CP.
(MAX) are reference levels for
and V
= 0.8V and V
t
t
RAC are not violated.
CAC are not violated.
IH
IH
t
and V
T = 5ns for FPM and 2.5ns
) in a monotonic manner.
SS
DD
.
t
AA and
= +3.3V; f = 1 MHz.
t
OH
IL
REF refresh
(or between V
= 2V.
t
t
RCD (MAX)
RAD (MAX)
t
CAC must
IH
t
t
RCD
RAD
and
IL
15
18. Either
19.
20. A HIDDEN REFRESH may also be performed after
21. LATE WRITE and READ-MODIFY-WRITE cycles
22. These parameters are referenced to CAS# leading
23.
24. Column address changed once each cycle.
25. The 3ns minimum parameter guaranteed by design.
26. With the FPM option,
27. Applies to both FPM and EDO modules.
t
without the
must always be met.
cycle.
t
achieves the open circuit condition and is not
referenced to V
a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.
must have both
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE cycle.
The DQs will provide the previously read data if
CAS# remains LOW and OE# is taken back LOW after
t
back LOW, the DQs will remain open.
edge in EARLY WRITE cycles and WE# leading edge
in LATE WRITE or READ-MODIFY-WRITE cycles.
t
operating parameters.
WRITE cycles.
READ-MODIFY-WRITE cycles. If
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
the entire cycle. If
t
t
and the data output will contain data read from the
selected cell. If neither of the above conditions is met,
the state of data-out is indeterminate. OE# held HIGH
and WE# taken LOW after CAS# goes LOW result in a
LATE WRITE (OE#-controlled) cycle.
t
WRITE cycle.
RAS# or CAS# signal to transition HIGH. In compari-
son,
latter of the RAS# and CAS# signals to transition
HIGH.
AA (
OFF (MAX) defines the time at which the output
OEH is met. If CAS# goes HIGH prior to OE# going
WCS,
RWD (MIN),
CWD (MIN), the cycle is a READ-MODIFY-WRITE
CWD and
t
OFF on an EDO option is determined by the
NONBUFFERED DRAM DIMMs
t
RAC and
t
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RCH or
RWD,
t
AWD are not applicable in a LATE
t
RAD (MAX) limit,
t
t
AWD and
AWD
t
OH
t
RWD,
t
t
RRH must be satisfied for a READ
CAC no longer applied). With or
OD and
t
or V
WCS <
t
t
t
OL
AWD and
t
OFF is determined by the first
WCS applies to EARLY
AWD (MIN) and
.
t
t
OEH met (OE# HIGH
CWD are not restrictive
t
WSC (MIN) and
t
AA,
2, 4 MEG x 72
t
CWD apply to
t
WCS
t
RAC and
t
WCS,
1998, Micron Technology, Inc.
t
CWD
t
WCS
t
RWD
t
RWD,
t
CAC