LPC47M112 SMSC Corporation, LPC47M112 Datasheet - Page 88

no-image

LPC47M112

Manufacturer Part Number
LPC47M112
Description
ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE
Manufacturer
SMSC Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LPC47M112-MC
Manufacturer:
SMSC
Quantity:
2 592
Part Number:
LPC47M112-MC
Manufacturer:
SMSC
Quantity:
20 000
Part Number:
LPC47M112-MW
Manufacturer:
SMSC
Quantity:
2 014
Part Number:
LPC47M112-MW
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
LPC47M112-MW
Manufacturer:
SMSC
Quantity:
20 000
Enhanced Super I/O Controller with LPC Interface
Datasheet
4.
5.
6.
7.
8.
SMSC DS – LPC47M112
Chip asserts nDATASTB or nADDRSTRB indicating that PData bus contains valid information, and the WRITE
signal is valid.
Peripheral deasserts nWAIT, indicating that any setup requirements have been satisfied and the chip may begin the
termination phase of the cycle.
a)
b)
Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and
acknowledging the termination of the cycle.
Chip may modify nWRITE and nPDATA in preparation for the next cycle.
The chip deasserts nDATASTB or nADDRSTRB, this marks the beginning of the termination phase. If it has
not already done so, the peripheral should latch the information byte now.
The chip latches the data from the internal data bus for the PData bus and drives the sync that indicates that no
more wait states are required followed by the TAR to complete the write cycle.
Page 88
Rev. 02/02/2005

Related parts for LPC47M112