LPC47M112 SMSC Corporation, LPC47M112 Datasheet - Page 166

• Manufacturer Part Number: LPC47M112
• Description: ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with LPC Interface
Datasheet
SMSC DS – LPC47M112
Power Mgmt
Default = 0x00
on VCC POR,
VTR POR and
HARD RESET
OSC
Default = 0x44, on
on VCC POR,
VTR POR and
HARD RESET
Chip Level
Vendor Defined
Configuration
Address Byte 0
Default
=0x2E (Sysopt=0)
=0x4E (Sysopt=1)
on VCC POR and
HARD RESET
Configuration
Address Byte 1
Default = 0x00
on VCC POR and
HARD RESET
Default = 0x00
on VCC POR,
SOFT RESET and
HARD RESET
Chip Level
Vendor Defined
TEST 6
Default = 0x00, on
VCC POR and
VTR POR
REGISTER
REGISTER
ADDRESS
ADDRESS
0x2A R/W
0x23 R/W
0x24 R/W
0x25
0x26
0x27
0x28
0x29
Bit[0] FDC
Bit[1] Reserved
Bit[2] Reserved
Bit[3] Parallel Port
Bit[4] Serial Port 1
Bit[5] Serial Port 2
Bit[6] Serial Port 3
Bit[7] Reserved (read as 0)
For each bit above (except Reserved)
= 0
= 1
Bit[0] Reserved
Bit [1] PLL Control
= 0
= 1
Bits[3:2] OSC
= 01
= 10
= 00
= 11
Bit [5:4] Reserved, set to zero
Bit [6] 16-Bit Address Qualification
= 0
= 1
Note: For normal operation, bit 6 should be set.
Bit[7] Reserved
Reserved - Writes are ignored, reads return 0.
Bit[7:1] Configuration Address Bits [7:1]
Bit[0] = 0
See Note 1
Bit[7:0] Configuration Address Bits [15:8]
See Note 1
Bits[7:0] Reserved - Writes are ignored, reads return
0.
Reserved - Writes are ignored, reads return 0.
Test Modes: Reserved for SMSC. Users should not
write to this register, may produce undesired results.
Intelligent Pwr Mgmt off
Intelligent Pwr Mgmt on
Osc is on, BRG clock is on.
Same as above (01) case.
Osc is on, BRG Clock Enabled.
Osc is off, BRG clock is disabled.
12-Bit Address Qualification
16-Bit Address Qualification
PLL is on (backward Compatible)
PLL is off
Page 166
DESCRIPTION
DESCRIPTION
STATE
STATE
C
C
C
C
Rev. 02/02/2005