LPC47M112 SMSC Corporation, LPC47M112 Datasheet - Page 66

• Manufacturer Part Number: LPC47M112
• Description: ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with LPC Interface
Datasheet
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Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt
Identification Register (refer to Interrupt Control Table). When the CPU accesses the IIR, the Serial Port freezes all
interrupts and indicates the highest priority pending interrupt to the CPU. During this CPU access, even if the Serial Port
records new interrupts, the current indication does not change until access is completed. The contents of the IIR are
described below.
Bit 0
This bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending.
When bit 0 is a logic "0", an interrupt is pending and the contents of the IIR may be used as a pointer to the appropriate
internal service routine. When bit 0 is a logic "1", no interrupt is pending.
Bits 1 and 2
These two bits of the IIR are used to
interrupt pending as indicated by the
Bit 3
In non-FIFO mode, this bit is a logic
along with bit 2 when a timeout
Bits 4 and 5
These bits of the IIR are always logic
Bits 6 and 7
These two bits are set when the FIFO CONTROL Register bit 0 equals 1.
SMSC DS – LPC47M112
Receiver Line Status (highest priority)
Received Data Ready
Transmitter Holding Register Empty
MODEM Status (lowest priority)
MODE
ONLY
BIT 3
FIFO
0
0
0
1
BIT 2
IDENTIFICATION
0
1
1
1
INTERRUPT
REGISTER
BIT 1
0
1
0
0
BIT 0
1
0
0
0
PRIORITY
Highest
Second
Second
Bit 7
LEVEL
0
0
1
1
Table 29 - Interrupt Control
-
Bit 6
0
1
0
1
INTERRUPT SET AND RESET FUNCTIONS
None
Receiver
Status
Received Data
Available
Character
Timeout
INTERRUPT
Page 66
Trigger Level (BYTES)
TYPE
RCVR FIFO
Line
14
1
4
8
None
Overrun Error,
Parity Error,
Framing Error or
Break Interrupt
Receiver Data
Available
No Characters
Have Been
INTERRUPT
SOURCE
identify
Interrupt Control Table.
"0". In FIFO mode this bit is set
interrupt is pending.
"0".
Reading the Line
Status Register
Read Receiver
Buffer or the FIFO
drops below the
trigger level.
Reading the
Receiver Buffer
INTERRUPT
the
CONTROL
RESET
-
highest
Rev. 02/02/2005
priority