LPC47M112 SMSC Corporation, LPC47M112 Datasheet - Page 143

• Manufacturer Part Number: LPC47M112
• Description: ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with LPC Interface
Datasheet
SMSC DS – LPC47M112
SMI_STS2
Default = 0x00
SMI_STS3
Default = 0x00
SMI_STS4
Default = 0x00
(Note 6)
SMI_STS5
Default = 0x00
N/A
SMI_EN1
Default = 0x00
on VTR POR
on VTR POR
on VTR POR
on VTR POR
on VTR POR
NAME
REG OFFSET
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(hex)
(R)
11
12
13
14
15
16
SMI Status Register 2
This register is used to read the status of the SMI inputs.
Bit[0] MINT. Cleared at source.
Bit[1] KINT. Cleared at source.
Bit[2] IRINT. This bit is set by a transition on the IR pin
(IRRX or IRRX2 as selected in CR L5-F1-B6 i.e., after the
MUX). Cleared by a read of this register.
Bit[3] Reserved
Bit[4] P12. Cleared at source.
Bit[7:5] Reserved
SMI Status Register 3
This register is used to read the status of the SMI inputs.
The following bits are cleared on a write of ‘1’.
Bit[0] GP20
Bit[1] GP21
Bit[2] GP22
Bit[3] Reserved
Bit[4] GP24
Bit[5] GP25
Bit[6] GP26
Bit[7] GP60
SMI Status Register 4
This register is used to read the status of the SMI inputs.
The following bits are cleared on a write of ‘1’.
Bit[0] GP30
Bit[1] GP31
Bit[2] GP32
Bit[3] GP33
Bit[4] GP41
Bit[5] GP42
Bit[6] GP43
Bit[7] GP61
SMI Status Register 5
This register is used to read the status of the SMI inputs.
The following bits are cleared on a write of ‘1’.
Bit[0] GP54
Bit[1] GP55
Bit[2] GP56
Bit[3] GP57
Bit[4] Reserved
Bit[5] Reserved
Bit[6] FAN_TACH1
Bit[7] FAN_TACH2
Reserved – reads return 0
SMI Enable Register 1
This register is used to enable the different interrupt sources
onto the group nSMI output.
1=Enable
0=Disable
Bit[0] Reserved
Bit[1] EN_PINT
Bit[2] EN_U2INT
Bit[3] EN_U1INT
Bit[4] EN_FINT
Bit[5] EN_MPU-401 INT
Bit[6] Reserved
Bit[7] Reserved (Note 7)
Page 143
DESCRIPTION
Rev. 02/02/2005